Resistive-Network BIST for MOSFET ESD Leakage Detection

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Solution Overview

Problem

Integrated circuits (ICs) are vulnerable to electrostatic discharge (ESD) damage, particularly as semiconductor process technology nodes advance, making it difficult to detect and address ESD-induced soft failures that can lead to latent defective performance and reduced long-term reliability.

Innovation Solution

A built-in self-tester (BIST) with resistive-network cell regions and a switching arrangement is used to detect ESD damage by measuring leakage currents, allowing for the identification of ICs susceptible to ESD-induced soft failures, thereby improving the detection of ESD-induced soft failures and enhancing the long-term reliability of ICs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional testing methods are used, then manufacturing process is simple, but ESD-induced soft failures cannot be detected

Engineering Contradiction:
Improvedetection capabilityVSAvoidtester structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The BIST device is segmented into functional modules: resistive-network cell regions for generating reference currents, switching arrangements for selecting test modes, and leakage current measurement circuits for detecting ESD damage. This modular segmentation enables precise measurement of leakage currents in the nanoampere to microampere range while maintaining manageable device complexity through organized functional blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The BIST device performs preliminary self-testing during fabrication before die separation, using built-in resistive-network cell regions to generate reference currents that flow through MOSFETs under test. This preliminary action detects ESD-induced soft failures early in the manufacturing process, preventing defective units from proceeding to final testing and reducing waste.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If advanced semiconductor process technology is used, then IC performance is improved, but vulnerability to ESD damage increases

Engineering Contradiction:
Improvelong-term reliabilityVSAvoidESD damage susceptibility
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The BIST device performs preliminary self-testing during fabrication before die separation, using built-in resistive-network cell regions to generate reference currents that flow through MOSFETs under test. This preliminary action detects ESD-induced soft failures early in the manufacturing process, preventing defective units from proceeding to final testing and reducing waste.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The BIST device measures leakage currents through MOSFETs and compares them against reference currents generated by resistive-network cell regions. When leakage current exceeds the reference current, indicating ESD damage, the device generates a failure signal. This feedback mechanism enables real-time detection and classification of ESD-induced soft failures, allowing for selective elimination of defective units to improve long-term reliability.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If leakage current measurement is performed, then ESD damage is detected, but measurement precision requirement increases

Engineering Contradiction:
Improveleakage current detection accuracyVSAvoidmeasurement challenge
Core Design Contradiction:
Measurement precisionVSDifficulty of detecting and measuring

Solution Approach 1:

The BIST device is segmented into functional modules: resistive-network cell regions for generating reference currents, switching arrangements for selecting test modes, and leakage current measurement circuits for detecting ESD damage. This modular segmentation enables precise measurement of leakage currents in the nanoampere to microampere range while maintaining manageable device complexity through organized functional blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The BIST device changes measurement parameters by switching between different test modes: flowing reference currents through MOSFETs under test, measuring resulting voltage drops, and comparing against threshold values. The switching arrangement selectively couples resistive-network cell regions to different MOSFETs, enabling systematic measurement of leakage currents across multiple devices with consistent precision.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The BIST effectively detects leakage currents in the range of nanoamperes to microamperes, enabling the identification of ICs prone to ESD-induced soft failures, which improves the long-term reliability of ICs by eliminating susceptible units from the population.

Implementation Method 1

The BIST is configured to detect leakage currents in the range of nanoamperes to microamperes, enabling the identification of ICs prone to ESD-induced soft failures

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20250012844A1Resistive-network cell region, built-in self-tester including same, semiconductor device including same, method of operating same and method of manufacturing same
Publication Date: 2025.01.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250012844A1 patent drawing
  • US20250012844A1 patent drawing
  • US20250012844A1 patent drawing

AI summary

A built-in self-tester (BIST) of a semiconductor device including: an input/output (I/O) circuit including an output buffer and an input buffer, an output of the output buffer being coupled at an I/O terminal to an input of the input buffer, the I/O terminal being configured to receive or provide an external I/O signal; one or more resistive-network cell regions arranged to affect a reference current received at the I/O terminal; and a switching arrangement configured to selectively couple the one or more resistive-network cell regions alternatively to a first reference voltage during a first phase or a second reference voltage during a second phase, the switching arrangement being further configured to determine electrostatic discharge (ESD) damage to metal-oxide-semiconductor (MOS) transistors included in the semiconductor device based on (1) phase and (2) an output signal of the input buffer