Resistive SAR ADC Architecture for Fewer Conversion Cycles

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current SAR ADCs face issues with large size, limited bandwidth, high current consumption, and require N+1 or N+2 cycles for conversion due to capacitive and current mode DACs, respectively.

Innovation Solution

A system comprising a sample and hold device, a voltage-to-current converter, a resistive digital-to-analog converter (R-DAC), and a comparator, where the R-DAC generates a differential voltage signal based on current flowing through variable resistances, allowing successive approximation to control resistance values for subsequent cycles, reducing the number of conversion cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If capacitive DAC is used in SAR ADC, then the ADC can be implemented, but the size becomes large and bandwidth is limited

Engineering Contradiction:

ImproveADC functionalityVSAvoidDAC size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the fundamental parameter of the DAC from capacitive to resistive implementation. By using resistive elements instead of capacitive elements, the DAC achieves smaller size while maintaining the required functionality for SAR ADC operation.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If capacitive DAC is used in SAR ADC, then the ADC can be implemented, but the bandwidth is limited leading to high current consumption

Engineering Contradiction:

ImproveADC functionalityVSAvoidcurrent consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the fundamental parameter of the DAC from capacitive to resistive implementation. By using resistive elements instead of capacitive elements, the DAC achieves wider bandwidth which directly reduces the current consumption required for high-speed operation.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If traditional SAR ADC conversion algorithm is used, then conversion can be completed, but N+1 or N+2 cycles are required

Engineering Contradiction:

Improveconversion accuracyVSAvoidconversion time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary action by pre-calculating and storing lookup tables (LUTs) that contain pre-determined conversion results. During actual conversion, the system queries these pre-computed tables rather than performing the full N+1 or N+2 cycle conversion algorithm, significantly reducing the time required while maintaining accuracy.

Inventive Principle:

Principle #10Preliminary action

4Reliability

If current mode DAC is used in SAR ADC, then the ADC can be implemented, but noise from active current sources increases and current consumption remains high

Engineering Contradiction:

ImproveADC functionalityVSAvoidnoise

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent substitutes the mechanical/electrical system of active current sources with a resistive system. By replacing active current mode DAC with passive resistive DAC, the harmful noise generated by active current sources is eliminated while maintaining the required DAC functionality.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the number of cycles required for conversion, enhancing speed and reducing power consumption, potentially achieving an 11% speed advantage by completing an 8-bit conversion in 8 cycles instead of 9, while maintaining low power and small area.

Implementation Method 1

The voltage-to-current converter is configured to convert the input voltage signal into a current

Methodology Applied

Scientific EffectVoltage-to-current conversion: Conduction (electrical)

Implementation Method 2

A second differential voltage is generated based on the differential current flowing through parallel-coupled respective first and second variable resistances

Methodology Applied

Scientific EffectOhm's Law: Ohm's Law

Data Source

PatentUS7642946B2Successive approximation analog to digital converter

Publication Date: 2010.01.05 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A system and method are provided allowing for successive approximation analog to digital conversion. A first differential voltage is sampled and held during a first cycle. The first differential voltage is converted to a differential current. A second differential voltage is generated based on the differential current flowing through parallel-coupled respective first and second variable resistances. First and second portions of the second differential voltage are compared to produce a comparison result therefrom. Successive approximation is used to generate a signal based on the comparison result, the signal being an output signal and being used to control resistances of respective ones of the first and second variable resistances during subsequent cycles.