Resistive Switch Array Routing Under Programming Current Constraints
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Solution Overview
Problem
Existing Field Programmable Gate Arrays (FPGAs) face limitations in utilizing resistive switch arrays due to programming challenges, such as non-uniform voltages and power constraints, which restrict the number of connections that can be programmably selected between routing resources and logic elements, leading to inefficient use of routing resources.
Innovation Solution
Implementing a single level of programmable selection circuitry using resistive switches, coupled with local column drivers and power buffers, and employing current source drivers to maintain uniform current through resistive switches, along with a method to generate programming vectors that account for power constraints, allowing for efficient programming of large resistive switch arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple levels of selection circuits (LIM, LEIM, DIM) are used to route signals, then routing flexibility is improved, but device complexity increases and the percentage of available connections decreases
Solution Approach 1:
The routing architecture is segmented into distinct functional blocks (logic array blocks) with standardized interfaces. Each LAB contains its own selection circuits and logic elements, allowing independent configuration. This segmentation enables complex routing functionality to be achieved through composition of simpler, reusable building blocks rather than requiring a monolithic complex selection circuit.
Solution Approach 2:
The patent transitions from traditional multi-level hierarchical selection circuits to a two-dimensional array architecture where logic elements are arranged in rows and columns with direct access to routing resources. This dimensional reorganization allows any logic element to access any routing line through a single-level selection process, eliminating the need for multiple cascaded selection levels while maintaining full routing flexibility.
2Adaptability or versatility
If CRAM elements and pass gate transistors are used for programming selection circuits, then programmability is achieved, but die area consumption increases and connection percentage decreases
Solution Approach 1:
The patent extracts the programming function from traditional CRAM-based configuration memory and implements it directly within the logic elements using simple latch circuits. Each logic element contains its own configuration latches that can be programmed independently, eliminating the need for separate CRAM blocks and reducing die area while maintaining full programmability.
Solution Approach 2:
The patent replaces expensive, area-intensive CRAM elements with simple, low-cost latch circuits that consume minimal die area. These latches are designed to be reconfigurable and can be programmed multiple times, providing a cost-effective alternative to traditional configuration memory while enabling higher density logic element arrays.
3Area of stationary object
If resistive switch arrays are implemented in FPGAs, then area efficiency is improved, but programming challenges (non-uniform voltages, power constraints) worsen
Solution Approach 1:
The patent implements local configuration memory and control circuits within each logic array block to provide localized programming capability. This allows voltage and current characteristics to be optimized for each local region, compensating for variations in resistive switch characteristics and ensuring uniform programming across the entire array despite differences in distance from global power sources.
Solution Approach 2:
The patent incorporates feedback mechanisms in the programming circuitry that monitor voltage and current levels during configuration operations. This feedback allows the system to dynamically adjust programming parameters to compensate for non-uniform voltage distribution across the resistive switch array, ensuring reliable and uniform programming of all switches regardless of their position in the array.
Data Source
AI summary
Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein.