Multi-bit Full Adder Using Resistive-Switching Cross-bar Array
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current digital circuits require a large number of transistors for multi-bit adders, leading to increased chip area and power consumption, making it difficult to achieve efficient and compact full adder designs.
Innovation Solution
A multi-bit full adder is implemented using a cross-bar array of resistive-switching devices, where data is stored in resistive-switching units with multiple resistance states, allowing for nonvolatile storage of sums and carry values, significantly simplifying the circuit and reducing transistor requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS logical circuit is used to achieve multi-bit adder, then the adder can perform addition operations, but the number of transistors increases and chip area becomes large
Solution Approach 1:
The patent replaces the mechanical transistor-based CMOS logical circuit with a resistive-switching device-based cross-bar array. The resistive-switching devices use electrical resistance states (high and low resistance) to represent binary values, fundamentally changing the physical basis of logic operations from transistor switching to resistance state manipulation. This substitution dramatically reduces the number of components needed for multi-bit addition operations.
Solution Approach 2:
The cross-bar array structure provides multi-functionality where the same array can perform multiple addition operations by reconfiguring the resistive-switching devices. The diagonal elements store sum results while adjacent elements store carry values, allowing the system to handle multiple bits of addition simultaneously within a compact structure that serves multiple computational purposes.
2Productivity
If CMOS logical circuit is used to achieve multi-bit adder, then the adder can perform addition operations, but the number of transistors increases and power consumption increases
Solution Approach 1:
The patent replaces the power-intensive CMOS transistor switching mechanism with a resistive-switching device mechanism that uses minimal power to maintain resistance states. The resistive-switching devices store information in their resistance states without requiring continuous power supply, and only consume power during state transitions, dramatically reducing overall power consumption compared to CMOS circuits that require continuous power for maintaining logic states.
Solution Approach 2:
The patent changes the fundamental operating parameter from voltage-based CMOS switching to resistance-based state storage. By using high and low resistance states to represent binary 0 and 1, the system achieves logic operations with minimal power consumption, as the resistance states are maintained without continuous energy input, unlike voltage states in CMOS circuits.
3Area of stationary object
If resistive-switching devices are used in cross-bar array, then chip area is reduced and transistor requirements are simplified, but the devices must maintain multiple stable resistance states
Solution Approach 1:
The patent changes the operating parameter from binary voltage levels to multi-level resistance states. The resistive-switching devices are designed to stably maintain at least four distinct resistance states (R1, R2, R3, R4) which are used to represent different binary values. This parameter change enables compact representation of multiple bits while maintaining reliability through the inherent stability of resistance states in resistive-switching devices.
Solution Approach 2:
The patent applies preliminary actions by pre-setting the resistive-switching devices to specific resistance states before computation. The diagonal elements are prepared to store sum results and adjacent elements are prepared to store carry values in their respective resistance states, ensuring that the computation can proceed reliably without needing to re-establish these states during the addition operation.
4Quantity of substance
If resistive-switching devices store data in multiple resistance states, then data storage capacity increases, but the complexity of reading and writing data increases
Solution Approach 1:
The patent applies local quality by assigning specific functions to specific locations in the cross-bar array. Diagonal elements (Ri,i) are dedicated to storing sum results, while adjacent elements (Ri,i+1 and Ri+1,i) are dedicated to storing carry values. This spatial differentiation simplifies the reading and writing operations, as the control circuit only needs to address specific locations for specific operations, reducing the overall complexity despite the multi-state storage capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces chip area and power consumption while maintaining performance by utilizing a cross-bar array of resistive-switching devices for storing data and carry values, enhancing the reliability and accuracy of addition operations.
Implementation Method 1
The resistive-switching layer may have a resistive-switching under the excitation of a voltage or a current
Data Source
AI summary
The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of resistive-switching devices, wherein data of standard sums is stored on the principle diagonal of the cross-bar array in a nonvolatile manner, and carry data is stored in adjacent units on both sides of the principle diagonal. The carry data is stored according to whether the storage loop (crosstalk loop) is turned on. With the present disclosure, the multi-bit full adder circuit is significantly simplified. Thereby, additional circuits for generating a carry signal are reduced, the circuit delay and chip area are decreased, and the adder has an ability of nonvolatile storage.