Two-Terminal Resistive Switching Device Sidewall Protection
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Solution Overview
Problem
Current semiconductor memory devices face challenges such as short channel effects, sub-threshold slope non-scaling, and high power consumption as they approach sizes less than 100 nm, and existing non-volatile random access memory devices like Fe-RAM, MRAM, and PCRAM have limitations in CMOS compatibility, size, and reliability.
Innovation Solution
A method and structure for a two-terminal switching device using noble metals like platinum and silver for electrodes, with a specific fabrication process that avoids exposing the sidewalls of the switching material during etching, forming a resistive switching device in a crossbar configuration to prevent electrical shorts and enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional transistor scaling is continued to achieve smaller device sizes, then device density is improved, but short channel effects and power dissipation increase
Solution Approach 1:
The patent replaces the conventional transistor-based mechanical switching mechanism with a resistive switching device that uses electrical resistance changes in a switching material layer. This substitution eliminates short channel effects and sub-threshold slope issues inherent in scaled transistors, enabling continued device miniaturization without the associated reliability degradation and power dissipation problems.
2Reliability
If existing non-volatile RAM devices (Fe-RAM, MRAM, PCRAM) are used, then non-volatile memory functionality is achieved, but CMOS compatibility and fabrication integration are compromised
Solution Approach 1:
The patent designs a resistive switching device structure and fabrication process that is universally compatible with existing CMOS manufacturing techniques. The device uses standard CMOS-compatible materials and processes (such as atomic layer deposition for dielectric layers and standard etching techniques), allowing the same fabrication line to produce both CMOS logic circuits and non-volatile memory devices without requiring separate specialized manufacturing facilities.
3Productivity
If sidewalls of switching material are exposed during etching process, then etching completion is achieved, but electrical shorts between electrodes occur
Solution Approach 1:
The patent applies a protective coating on the sidewalls of the switching material structure before performing the etching process. This preliminary protective action prevents etchant from attacking the sidewalls and causing electrical shorts, while still allowing the etching process to complete the necessary patterning of the device structure. The protective coating is subsequently removed after etching is complete.
4Area of moving object
If device size is reduced below 100 nm, then device density is improved, but sub-threshold slope non-scaling and power dissipation increase
Solution Approach 1:
The patent replaces the field-effect transistor mechanism with a resistive switching mechanism that does not suffer from sub-threshold slope degradation at small dimensions. The resistive switching device maintains low power dissipation even when scaled below 100 nm because it operates through ohmic resistance changes rather than field effect modulation, eliminating the power dissipation issues that plague scaled transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enables the fabrication of scalable, non-volatile resistive switching memory devices with fast switching characteristics and improved reliability by preventing shorts between electrodes, thus enhancing device yield and performance.
Implementation Method 1
The two terminal switching device can be used as a non-volatile resistive switching memory with random access and fast switching characteristics
Data Source
AI summary
A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A top wiring material including a conductive material is formed overlying at lease the opening region such that the conductive material is in direct contact with the switching element. A second etching process is performed to form at least a top wiring structure. In a specific embodiment, the side region of the first structure including a first side region of the switching element is free from a contaminant conductive material from the second etching process.