Resistive Switching Device with Intermediate Electrode Layer
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Solution Overview
Problem
The semiconductor industry faces limitations with Flash memory, prompting the need for alternative memory technologies, and existing emerging memories such as MRAM, FeRAM, PCRAM, metal oxide based memories, and ionic memories require innovations to become viable alternatives.
Innovation Solution
A resistive switching device is developed comprising a first electrode, a switching layer with minimal copper and silver content, a conductive amorphous intermediate electrode layer, and a second electrode, where the switching layer can modulate resistance with an applied electric field, enabling non-volatile memory functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional emerging memories (MRAM, FeRAM, PCRAM, metal oxide based memories, ionic memories) are used, then memory functionality is achieved, but uniformity and stability are insufficient
Solution Approach 1:
The patent changes the chemical composition parameters of the switching layer by minimizing copper and silver content to less than 0.01%, and controlling copper and silver content in electrodes to less than 5%. This parameter change improves uniformity and stability while maintaining resistive switching functionality, resolving the contradiction between reliability and viability.
Solution Approach 2:
The patent introduces an intermediate electrode layer between the switching layer and the top electrode. This intermediary layer serves as a buffer that improves interface quality and electrical contact, thereby enhancing overall device uniformity and stability without compromising the memory functionality.
2Reliability
If copper and silver content is increased in switching layer and electrodes, then conductivity is improved, but uniformity deteriorates
Solution Approach 1:
The patent optimizes the copper and silver content parameters to specific ranges (less than 0.01% in switching layer, less than 5% in electrodes). This controlled parameter change achieves a balance where sufficient conductivity is maintained while uniformity is significantly improved, resolving the contradiction between these two properties.
Solution Approach 2:
The patent applies different copper and silver content specifications to different layers: the switching layer has strict limits (less than 0.01%) for uniformity, while electrodes have more lenient limits (less than 5%) to maintain conductivity. This local quality differentiation resolves the contradiction by optimizing each layer's composition for its specific function.
3Productivity
If Flash memory is used, then mainstream non-volatile memory functionality is achieved, but scalability and performance improvement are limited
Solution Approach 1:
The patent replaces conventional Flash memory mechanisms with resistive switching mechanisms in an emerging memory device. This substitution enables new performance characteristics and scaling potential that overcome Flash memory limitations, while maintaining non-volatile memory functionality. The resistive switching mechanism allows for simpler device structures that can be scaled more effectively.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The resistive switching device effectively modulates resistance between low and high states, providing a viable alternative for memory technology by leveraging a copper- and silver-minimized structure for improved uniformity and stability.
Implementation Method 1
a switching layer disposed over the first electrode... The switching layer comprises less than 0.01% of copper and silver... effectively modulates resistance between low and high states
Data Source
AI summary
In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.