Resistive Switching Memory Intrinsic Error Suppression
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Solution Overview
Problem
Current resistive-switching memory technologies face challenges in generating high randomness and unique data sequences for applications like identification and random number generation, as existing methods struggle to leverage the stochastic characteristics of resistive switching devices effectively.
Innovation Solution
The implementation of a method that aggregates multiple resistive switching memory cells to define a bit with desirable non-correlation characteristics, utilizing physical unclonable features (PUF) and random number generation (RNG) bits, where electrodes are coupled to a common voltage source and second electrodes are electrically shorted to a shared node, allowing for intrinsic inhibition of a second memory cell following programming of a first memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple resistive switching memory cells are aggregated to define a bit with desirable non-correlation characteristics, then the randomness and uniqueness of data sequences are improved, but the device complexity increases
Solution Approach 1:
The bit is segmented into multiple resistive switching memory cells (e.g., two or more cells) that are aggregated together. Each cell contributes to the overall non-correlation characteristics, and the segmentation allows the system to leverage stochastic variations across multiple independent cells to generate highly random data sequences with low bit error rates.
2Reliability
If second electrodes of memory cells are electrically shorted to a shared node to enable intrinsic inhibition, then the programming reliability is improved, but the circuit complexity increases
Solution Approach 1:
The second electrodes of multiple memory cells are merged and electrically shorted to a shared common node. This merging enables intrinsic inhibition functionality where programming one cell automatically affects the voltage state of other cells sharing the same common node, thereby improving programming reliability through cross-cell feedback without requiring additional control circuitry for each individual cell.
3Ease of manufacture
If a common voltage source is used to apply program signals across multiple memory cells, then the manufacturing simplicity is improved, but the measurement precision of individual cell states deteriorates
Solution Approach 1:
While the voltage source is common, the measurement and control are segmented by individually coupling each first electrode of the memory cells to the common voltage source through separate control circuitry. This allows independent monitoring and precise measurement of each cell's state (programmed or unprogrammed) even though the same voltage source is used, thereby maintaining measurement precision while simplifying manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach generates highly non-correlated data sequences with low bit error rates, suitable for identification and security applications, and can be reliably read multiple times, achieving high entropy and randomness comparable to high-quality cryptographic random number sources.
Implementation Method 1
stochastic characteristics of resistive-switching structures have been proposed by the inventor as suitable for generating non-correlated data for random number generation
Implementation Method 2
concurrently applying a program signal having a voltage magnitude and a cycle duration from the common voltage source across the respective first electrodes of the plurality of memory cells
Implementation Method 3
electrically shorting respective second electrodes of the plurality of memory cells to a shared node, and concurrently applying a program signal
Data Source
AI summary
Embodiments of the present disclosure provide intrinsic program suppression of a non-programmed two-terminal resistive switching memory cell of a plurality of memory cells defining an identifier bit, such as a physical unclonable feature (PUF) bit. Differential programming applies a program signal to a plurality of resistive switching memory cells and derives a value for the identifier bit from which cell(s) becomes programmed. However, where more than an expected number of cells become programmed, an invalid value can occur. Disclosed intrinsic program suppression mitigates or avoids the invalid result by very rapidly reducing the program signal to a non-programmed cell(s) in response to another cell(s) becoming programmed. In an embodiment, intrinsic program suppression can be implemented by programming the plurality of memory cells electrically in parallel and shorting second terminals of the plurality of memory cells at a common node.