Resistive Switching Memory Dynamic Host Allocation PUF
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current resistive-switching memory technologies face challenges in characterizing and configuring subsets of resistive switching memory cells for diverse operations, such as random number generation and physical unclonable feature operations, which are essential for advanced memory applications but are not traditionally supported by non-volatile memory.
Innovation Solution
A memory device and method that enable characterization and configuration of resistive switching memory cells through trim instructions and a memory controller, allowing for operations like PUF, OTP, MTP, and RNG by decoding host commands and implementing specific operations on identified memory cells, leveraging stochastic physical characteristics for unique identification and security applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If resistive switching memory cells are used for traditional non-volatile memory operations, then storage capacity and non-volatility are improved, but the ability to perform diverse operations such as PUF, OTP, MTP, and RNG is limited
Solution Approach 1:
The patent implements dynamic host allocation of physical unclonable feature operations, allowing the memory device to switch between different operational modes (PUF, OTP, MTP, RNG, and traditional non-volatile memory operations) based on host commands. This dynamic reconfiguration enables a single resistive switching memory device to adapt to diverse application requirements without requiring separate dedicated hardware for each function, thereby resolving the contradiction between operational versatility and device complexity
Solution Approach 2:
The patent makes resistive switching memory cells universal by enabling them to perform multiple functions including traditional non-volatile storage, PUF operations, OTP operations, MTP operations, and random number generation. Through trim instructions and host command interpretation, the same physical memory cells can be configured for different operational modes, eliminating the need for separate specialized memory devices and achieving multi-functionality without proportionally increasing device complexity
2Reliability
If trim instructions are used to characterize memory cells for specific operations, then operational precision and reliability are improved, but the time and complexity of configuration increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring trim instructions during manufacturing or initialization that define memory cell characterizations and suitable operations. These trim instructions are stored in the memory device and automatically referenced when host commands are received, allowing rapid configuration without time-consuming characterization processes at runtime. The preliminary setup enables the device to quickly switch between operational modes while maintaining high reliability
Solution Approach 2:
The memory device performs self-service by automatically referencing stored trim instructions to configure memory cells based on received host commands. The device independently determines the appropriate operation mode (PUF, OTP, MTP, RNG, or traditional storage) and configures the specified memory cells without requiring external characterization equipment or manual intervention, thereby reducing configuration time while maintaining operational reliability
Data Source
AI summary
An integrated circuit device can be configured to characterize portions of a resistive switching device array according to one or more operational characterizations. The memory device can store trim instructions defining signal processes for implementing the operational characterizations. Examples of resistive switching device characterizations can include: a physical unclonable feature (PUF) memory characterization, a one-time programmable (OTP) memory characterization, a many-time programmable (MTP) memory characterization, and a random number generation (RNG) memory characterization, among others. The integrated circuit device can characterize portions of the resistive switching device array in response to an instruction from an external host device, exposing control over the selective characterization of the portions of the resistive switching device array to the external host device.