Resistive Test Structure for Semiconductor Process Variation Detection
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Solution Overview
Problem
Conventional test patterns in semiconductor manufacturing are not sensitive enough to reliably detect process variations, which can lead to lower yields due to feature dimensional and doping variations.
Innovation Solution
A resistive test structure is developed, featuring a semiconductor substrate with active regions, a gate stack, and electrical contacts that form an electrical short across the gate stack, allowing for more accurate measurement of resistance variations indicative of process changes, similar to the formation processes of MOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test patterns are used, then manufacturing simplicity is maintained, but measurement precision is insufficient to detect process variations
Solution Approach 1:
The test structure is segmented into multiple functional components: active regions, gate stacks, electrical contacts, and isolation regions. This segmentation allows each component to contribute specifically to the measurement function, enabling precise detection of process variations while maintaining a systematic and manageable structure.
Solution Approach 2:
The test structure uses the same formation processes as production MOS transistors, making it multi-functional. It can detect dimensional variations, doping variations, and thermal process variations, serving as a universal test solution for multiple types of process control needs.
2Reliability
If simple resistor test patterns are used, then device complexity is low, but reliability of process variation detection is insufficient
Solution Approach 1:
The test structure measures changes in electrical resistance parameters that result from process variations. By monitoring resistance changes in the active regions between electrical contacts, the structure reliably detects dimensional and doping variations while maintaining a relatively simple resistive measurement approach.
3Manufacturing precision
If conventional test patterns are used, then ease of manufacture is maintained, but manufacturing precision of process control is insufficient
Solution Approach 1:
The test structure is formed using preliminary actions that mirror production processes: active regions are doped, gate stacks are formed, and electrical contacts are created before final device fabrication. This preliminary formation allows process variations to be detected early while using the same manufacturing techniques as production devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a more robust method for detecting process variations by correlating resistance measurements with dimensional, doping, and thermal changes, enabling more reliable assessment and potential failure or passing of wafers based on acceptable variation ranges.
Implementation Method 1
a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack
Implementation Method 2
measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes
Data Source
AI summary
A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.