Symmetrical Resistor Array Layout for DAC Linearity Accuracy
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Solution Overview
Problem
The resistance gradient effect in resistor arrays of digital-to-analog converter circuits leads to increased differential nonlinearity (DNL) and integral nonlinearity (INL), reducing conversion accuracy, while existing layouts to mitigate these issues significantly increase routing complexity.
Innovation Solution
A resistor array circuit design with parallel first and second resistor circuit strings, each comprising sequentially coupled resistors with symmetrical resistance gradients, mitigates the resistance gradient effect without increasing routing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resistor array is divided into two arrays with the center as the symmetrical center to mitigate DNL and INL increase, then the conversion accuracy is improved, but the amount of routing in the resistor array is significantly increased
Solution Approach 1:
The resistor array is divided into multiple resistor circuits (first, second, third, and fourth resistor circuits) that are coupled in parallel. Each resistor circuit contains resistors with specific resistance values (R, 2R, 4R, etc.) arranged in a segmented structure. This segmentation allows the circuit to handle resistance gradient effects locally within each resistor circuit while maintaining overall conversion accuracy, without requiring complex routing between distributed components.
Solution Approach 2:
Each resistor circuit is designed with specific local characteristics where resistors are arranged with particular resistance values in specific positions. The first and second resistor circuits have resistors with first resistance values, while the third and fourth resistor circuits have resistors with second resistance values. This local quality differentiation allows each circuit segment to compensate for resistance gradient effects in its specific location, improving conversion accuracy without increasing routing complexity.
2Measurement precision
If resistors with different resistance values are used in the resistor array to compensate for resistance gradient effects, then the DNL and INL are reduced, but the manufacturing precision requirements are increased
Solution Approach 1:
The patent employs resistors with specifically changed parameter values (resistance values of R, 2R, 4R, and their complements) arranged in a systematic pattern. By changing the resistance parameters in a controlled manner across different resistor circuits and positions, the design compensates for resistance gradient effects. This systematic parameter change approach reduces linearity errors while maintaining manageable manufacturing precision requirements through the regular pattern of value changes.
3Measurement precision
If a symmetrical layout is used to mitigate resistance gradient effects, then the conversion accuracy is improved, but the area occupied by the resistor array is increased
Solution Approach 1:
Multiple resistor circuits are merged and coupled in parallel configuration, sharing common connection points and signal paths. The first, second, third, and fourth resistor circuits are combined such that they collectively implement the digital-to-analog conversion function. This merging approach allows the circuit to achieve symmetry-based compensation for resistance gradient effects while utilizing shared routing and compact arrangement, thereby reducing the overall area compared to fully separate symmetrical layouts.
Data Source
AI summary
A resistor array circuit comprises first and second resistor circuit strings is provided. The first and second resistor circuit strings are coupled in parallel, coupled to a signal output terminal, and configured to receive a bit signal. Each of the first and second resistor circuits comprises resistor circuits coupled sequentially, each resistor circuit comprises first, second and third resistors that are coupled sequentially and in series. The first and second resistors of each resistor circuit are coupled to the first resistor of an adjacent resistor circuit. The first, second, third resistors of each resistor circuit of the first resistor circuit string are sequentially arranged along a first direction. The third, second, first resistors of each resistor circuit of the second resistor circuit string are sequentially arranged along the first direction. Each of the first, second and third resistors has a resistance gradient increasing or decreasing along the first direction.