Resistor DAC Charge-Boost Circuit for Faster SAR ADC Settling
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Solution Overview
Problem
SAR ADCs face challenges in settling time and power consumption due to the large voltage steps and impedance jumps during the determination of the most significant bit, particularly in resistor-capacitor networks, which prolong the conversion process.
Innovation Solution
Incorporating a charge boost capacitor coupled to the midpoint of the resistive network in the SAR ADC, facilitating charge sharing to reduce the voltage step and impedance jump, thereby decreasing settling time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a resistor-capacitor network is used in SAR ADC for digital-to-analog conversion, then the conversion accuracy is improved, but the settling time increases and power consumption increases due to large voltage steps and impedance jumps during MSB determination
Solution Approach 1:
The resistor network is segmented into two parallel paths: a main resistor network and a charge boost network. The charge boost network contains resistors connected to a charge boost capacitor, creating separate charge transfer paths that allow independent control of voltage steps and charge distribution, thereby reducing settling time while maintaining conversion accuracy.
Solution Approach 2:
A charge boost capacitor is introduced as an intermediary element in the charge boost network. This capacitor acts as a mediator that provides additional charge during the MSB determination phase, reducing the voltage step size and impedance jump effects, which accelerates settling without compromising the accuracy provided by the main resistor-capacitor network.
2Measurement precision
If a resistor-capacitor network is used in SAR ADC for digital-to-analog conversion, then the conversion accuracy is improved, but the power consumption increases due to large voltage steps and impedance jumps during MSB determination
Solution Approach 1:
The power consumption is segmented and optimized by dividing the resistor network into two parallel paths. The charge boost network with its dedicated capacitor handles the high-power MSB determination, while the main resistor network operates at lower power for subsequent bits, reducing overall power consumption while maintaining conversion accuracy.
Solution Approach 2:
The charge boost capacitor serves as an energy intermediary that stores and releases charge during MSB determination. This reduces the direct power draw from the reference voltage sources during high-current transient periods, thereby reducing peak power consumption while maintaining the accuracy benefits of the resistor-capacitor network.
3Productivity
If large voltage steps are used during MSB determination in SAR ADC, then the conversion speed is improved, but the settling time increases and power consumption increases
Solution Approach 1:
The voltage step generation is segmented into two paths: the main resistor network provides the full-scale voltage steps for speed, while the charge boost network provides refined, smaller voltage steps for accurate MSB determination. This segmentation allows the system to achieve both fast conversion and short settling time by combining the advantages of both paths.
Solution Approach 2:
The voltage step size parameter is dynamically changed during MSB determination by switching between the main resistor network and the charge boost network. The charge boost network enables smaller, more precise voltage steps that reduce settling time, while maintaining the overall conversion speed through efficient bit determination sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The charge boost capacitor reduces settling time by approximately 50% and decreases power consumption, enhancing the conversion speed and efficiency of SAR ADCs.
Implementation Method 1
Incorporating a charge boost capacitor coupled to the midpoint of the resistive network in the SAR ADC, facilitating charge sharing to reduce the voltage step and impedance jump
Data Source
AI summary
Examples of this description provide for a circuit. In some examples, the circuit includes a resistive network, a least significant bit (LSB) capacitor selectively coupled via a switch to receive an analog input voltage or to a selected first tap in the resistive network, and a charge boost network coupled in parallel with the resistive network and to a midpoint of the resistive network. To determine a most significant bit of lower order bits of a digital representation of the analog input voltage, the charge boost network is coupled to the LSB capacitor.