Resistor Delay-Line TDC for High Resolution With Lower Chip Area
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) face challenges in achieving high resolution while maintaining a small chip size and reducing power consumption, particularly in implementing high-frequency all-digital phase locked loops, as they require larger chip sizes and increased power consumption.
Innovation Solution
A high-resolution TDC design incorporating two delay lines with resistors and comparators, along with an encoder, where the resistors are implemented using metal lines and via plugs to achieve small resistance values, and includes resolution control capacitor banks and delay time compensation units to optimize resolution and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a vernier delay line is used to increase resolution, then measurement precision is improved, but area of stationary object increases
Solution Approach 1:
The delay line is segmented into multiple sections with different delay characteristics. By dividing the delay line into segments and selectively activating them, the patent achieves high resolution without requiring a complete vernier delay line structure, thereby reducing chip area while maintaining measurement precision.
Solution Approach 2:
The delay elements are designed to serve multiple functions: they provide both delay functionality and resolution measurement capability. This multi-functionality eliminates the need for separate vernier delay lines, reducing overall chip area while maintaining high resolution performance.
2Measurement precision
If a vernier delay line is used to increase resolution, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of delay line sections, activating only the necessary segments for each measurement. This dynamic operation reduces overall power consumption compared to continuously operating complete vernier delay lines, while maintaining high resolution through selective section activation.
Solution Approach 2:
Instead of utilizing the full vernier delay line structure for all measurements, the patent employs partial action by activating only the minimum necessary delay sections required for achieving the desired resolution, thereby significantly reducing power consumption while maintaining measurement precision.
3Measurement precision
If a vernier delay line is used to increase resolution, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes unnecessary components from the traditional vernier delay line structure, retaining only the essential elements required for high-resolution measurement. This extraction simplifies the overall device complexity while preserving the core functionality that enables precise time difference measurement.
Solution Approach 2:
Instead of following the conventional vernier delay line approach with two complete delay lines, the patent inverts the methodology by using a single delay line with selectively activated sections. This inverted approach achieves the same resolution with reduced structural complexity.
Data Source
AI summary
A time-to-digital converter includes a first delay line, a second delay line, comparators, and an encoder. The first delay line includes first resistors coupled in series and receives a first signal through a start node. The second delay line includes second resistors coupled in series and receives a second signal through a node corresponding to an end node of the first delay line. The comparators compare first voltages of nodes on the first delay line with second voltages of corresponding nodes on the second delay line. The encoder generates a digital code based on outputs of the comparators. Therefore, the time-to-digital converter may decrease a chip size thereof and lower power consumption, and the time-to-digital converter may increase a range of a maximum delay time between two signals.