Resistor Dummy Active Areas for CMP Planarization Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits with shallow trench isolation (STI) process face issues with unpredictable thickness profiles and erratic resistance due to overpolishing in resistor areas, leading to variable resistance and temperature dependence in polysilicon resistors.
Innovation Solution
Incorporating resistor dummy active areas in STI field oxide to control the CMP process, preventing overpolishing and maintaining a desired thickness of field oxide, which is achieved by strategically placing dummy active areas with specific densities and configurations to stabilize the resistance of well and polysilicon resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a CMP process is used to planarize large areas of low active area density, then planarization is achieved, but overpolishing occurs producing thin field oxide with unpredictable thickness profiles
Solution Approach 1:
The patent introduces dummy active areas with specific patterns (e.g., 10-50 micrometer squares spaced 5-20 micrometers apart) to create local variations in CMP polishing behavior. These dummy structures are strategically placed in low active area density regions to modify the polishing pressure distribution, preventing overpolishing in resistor areas while maintaining planarization in other regions. This local modification approach resolves the contradiction by making the field oxide thickness uniform in critical resistor areas without sacrificing overall planarization capability.
2Quantity of substance
If dopants are implanted through thin field oxide, then doping occurs, but resistance becomes low and erratic due to excessive dopant penetration
Solution Approach 1:
The patent performs preliminary patterning of dummy active areas before dopant implantation to pre-establish the field oxide thickness profile. By creating these dummy structures ahead of time, the field oxide thickness is controlled in advance to be sufficient (e.g., 50-200 nanometers) in resistor areas, ensuring that subsequent dopant implantation does not penetrate excessively. This preliminary action prevents the contradiction between achieving adequate doping and maintaining precise resistance control.
3Quantity of substance
If polysilicon thickness is high and erratic on overpolished field oxide, then deposition is complete, but resistance becomes low and variable with undesired temperature dependence
Solution Approach 1:
The patent uses locally patterned dummy active areas to create spatially varying field oxide thickness, ensuring that resistor areas have sufficient thickness (50-200 nm) to support uniform polysilicon deposition. This local modification prevents overpolishing in resistor regions, thereby ensuring consistent polysilicon thickness and stable temperature dependence characteristics. The dummy structures are removed after serving their protective function, leaving uniform resistor characteristics.
Solution Approach 2:
The patent introduces dummy active areas as a protective cushion before polysilicon deposition. These dummy structures prevent overpolishing that would otherwise lead to thin and erratic field oxide, which in turn would cause high and variable polysilicon thickness. By providing this beforehand cushioning, the patent ensures stable polysilicon resistor characteristics including consistent temperature dependence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent and desired resistance values for both well and polysilicon resistors by maintaining a controlled thickness of field oxide, reducing variability and temperature dependence, thereby improving the reliability of integrated circuits.
Implementation Method 1
The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches
Implementation Method 2
Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor
Data Source
AI summary
An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.