Semiconductor Resistor Groove Masking for CMP Dishing Control
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Solution Overview
Problem
The damascene-gate process for semiconductor devices results in variations in resistor size due to dishing phenomena during chemical mechanical polishing (CMP), leading to inaccuracies in resistor formation, especially for analog circuits with large line widths.
Innovation Solution
A semiconductor device and method where a mask layer is formed separated from all side surfaces of the resistor groove by a predetermined distance to protect a uniform-thickness portion of the conductive layer, allowing for precise formation of the resistor using the damascene-gate process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a damascene process is used to form a wiring line by depositing conductive material in a wiring-line groove and removing excess material by CMP, then the wiring line can be formed with good planarity, but dishing phenomena occur during CMP that cause variations in resistor size and lead to inaccuracies in resistor formation
Solution Approach 1:
The patent applies preliminary action by forming a dummy gate electrode and dummy gate insulating film before the actual gate electrode formation. These dummy structures serve as placeholders that maintain the integrity of the CMP process, preventing dishing phenomena from affecting the final resistor dimensions. The dummy structures are removed after serving their protective function, leaving the resistor with accurate dimensions.
Solution Approach 2:
The patent uses dummy gate electrodes and dummy gate insulating films as intermediary structures during the manufacturing process. These intermediary elements absorb the harmful dishing effects during CMP, protecting the actual resistor structures from dimensional variations. The intermediaries are temporarily present during processing and then removed, having served their protective purpose.
2Reliability
If high-k films are used as gate insulating films to increase physical thickness, then leakage is reduced, but the films have low heat resistance and must be formed after high-temperature diffusion heat treatment
Solution Approach 1:
The patent applies preliminary action by performing high-temperature diffusion heat treatment to form source and drain regions before depositing the high-k gate insulating film. This sequence allows the heat treatment to complete without exposing the temperature-sensitive high-k film to high temperatures, thereby preserving both the leakage-reducing properties of the high-k film and the integrity of the thermal processing.
Solution Approach 2:
The patent inverts the conventional process sequence by forming the gate insulating film after the source and drain regions are established through high-temperature diffusion. Instead of forming the gate insulating film first and then performing heat treatment (which would damage the film), the process is reversed to protect the high-k film while still achieving the desired electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of resistors with high accuracy by preventing dishing and ensuring consistent resistance values, suitable for analog circuits.
Implementation Method 1
removing the conductive material deposited outside the groove by a method such as chemical mechanical polishing (CMP)
Implementation Method 2
depositing a conductive material in the wiring-line groove
Implementation Method 3
depositing a conductive material in the wiring-line groove
Data Source
AI summary
A semiconductor device includes a substrate, an insulating film disposed on the substrate, a resistor groove disposed in the insulating film, and a resistor disposed in the resistor groove. The resistor is separated from all side surfaces of the resistor groove by a predetermined distance.