Resistor Ladder DAC Switching to Reduce Differential Non-Linearity
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Solution Overview
Problem
Existing DAC circuits suffer from significant differential non-linearity (DNL) due to leakage current, leading to inaccurate signal conversion and high power consumption.
Innovation Solution
The implementation of a resistive ladder with two or more levels of switches and corresponding decoder circuits, where overlapping subsets of digital input bits are used to minimize switch flips, thereby reducing leakage current and DNL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DAC circuits use single-level switches for digital to analog conversion, then the circuit structure is simple, but differential non-linearity errors are significant due to leakage current
Solution Approach 1:
The patent divides the switching circuit into two levels: first-level switches controlled by a first decoder and second-level switches controlled by a second decoder. This segmentation allows independent optimization of each level, reducing leakage current effects on DNL while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent transitions from a single-level switching architecture to a two-level hierarchical switching architecture. This dimensional change in the circuit topology enables better control over leakage current paths and reduces their impact on differential non-linearity, while the hierarchical structure keeps complexity manageable through organized control stages.
2Measurement precision
If DAC circuits use multiple switches for signal conversion, then conversion accuracy can be improved, but leakage current increases leading to higher power consumption
Solution Approach 1:
The patent extracts and separates the control functions into two distinct decoder circuits that operate on different subsets of digital input bits. This extraction allows the circuit to achieve high conversion accuracy through multiple switches while minimizing simultaneous switch activations, thereby reducing leakage current and power consumption.
Solution Approach 2:
The patent uses overlapping subsets of digital input bits to control the two levels of switches, where each decoder handles a partial subset rather than all bits simultaneously. This partial action approach reduces the number of switches active at any given moment, decreasing leakage current while maintaining the necessary conversion accuracy through the coordinated action of both decoder levels.
Data Source
AI summary
An example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.