Resistor Ladder Phase Interpolation for Linear Clock Adjustment
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Solution Overview
Problem
Conventional timing circuits face challenges in achieving monotonic and linear phase interpolation, which is essential for clocking circuits like Clock/Data Recovery circuits and Spread Spectrum Phase Locked Loops, as existing solutions do not effectively implement resistor ladder-based phase adjustment.
Innovation Solution
A resistor ladder-based phase interpolation circuit comprising a reference circuit, a resistor ladder, and an output circuit that generates an adjusted clock signal by enabling tap resistors, using a reference signal, clock signal, phase signals, and a reset signal to achieve phase adjustment within a Phase Locked Loop or clock and data recovery circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional phase interpolation circuits are used, then phase adjustment capability is provided, but monotonic and linear operation is not achieved
Solution Approach 1:
The phase interpolation range is divided into multiple segments corresponding to different tap positions on the resistor ladder. Each tap position represents a specific phase shift increment, creating discrete phase steps that collectively cover the full interpolation range. This segmentation enables precise control over phase shift increments while maintaining monotonic progression through the resistor divider network.
Solution Approach 2:
The circuit changes the resistance parameter by selecting different tap positions on the resistor ladder. Each tap position corresponds to a specific resistance value, which directly controls the phase shift amount. By varying the resistance parameter in a monotonic sequence through tap selection, the circuit achieves linear phase interpolation with predictable and monotonic phase shift increments.
2Adaptability or versatility
If phase adjustment range is increased, then versatility is improved, but circuit complexity increases
Solution Approach 1:
The resistor ladder circuit serves multiple functions simultaneously: it acts as a voltage divider, a phase shift controller, and a reference for charge pump operation. The same resistor network enables both coarse phase adjustment through tap selection and fine phase adjustment through the charge pump, providing universal phase control capability without requiring separate circuits for different adjustment ranges.
Solution Approach 2:
The resistor ladder acts as an intermediary element that translates digital tap selection signals into analog voltage levels, which then control the charge pump current direction and magnitude. This intermediary mechanism enables the circuit to achieve wide phase adjustment range while maintaining simple digital control logic, as the resistor ladder handles the complex analog transformation automatically.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides monotonic and linear phase interpolation with adjustable phase resolution, enabling effective operation within PLL and CDR circuits by generating an adjusted clock signal with precise phase adjustments, addressing the limitations of conventional timing circuits.
Implementation Method 1
The resistor ladder may be configured to generate a tap voltage in response to the reference signal. The tap voltage may be generated by enabling one or more of a plurality of tap resistors.
Data Source
AI summary
An apparatus comprising a reference circuit, a resistor ladder, and an output circuit. The reference circuit may be configured to generate a reference signal in response to (i) a clock signal, (ii) a first phase signal and (iii) a second phase signal. The resistor ladder circuit may be configured to generate a tap voltage in response to the reference signal. The tap voltage may be generated by enabling one or more of a plurality of tap resistors. The output circuit may be configured to generate an adjusted clock signal in response to (i) the tap voltage, (ii) the clock signal, (iii) the first phase signal, (iv) the second phase signal, and (v) a reset signal. The adjusted clock signal may have an adjusted phase with respect to the clock signal.