Resistor Layer Layout for Micro-Loading Variation Control
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Solution Overview
Problem
In semiconductor devices with varying pattern densities, the micro-loading effect causes significant variations in resistance values of resistor elements, particularly exceeding 0.2% in highly precise analog circuits like digital-to-analog converters.
Innovation Solution
The semiconductor device incorporates a design with first and second resistor layers of varying widths and overlapping regions with a wiring layer, where the total area of overlapping regions for second resistor layers is minimized relative to their width, reducing variations by optimizing the layout and manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy patterns are formed in outer peripheral portions to reduce pattern density differences, then resistance value variations are reduced, but device area increases
Solution Approach 1:
The patent applies local quality by making the wiring layer width variable in different regions. Specifically, the wiring layer has a first width in regions overlapping with first resistor layers and a second width (smaller than the first width) in regions overlapping with second resistor layers. This localized variation in wiring width compensates for the micro-loading effect on narrow resistor lines without requiring dummy patterns, thus reducing resistance variations while minimizing area increase.
Solution Approach 2:
The patent changes the physical parameter of the wiring layer width to counteract the micro-loading effect. By adjusting the wiring layer width based on the local pattern density and resistor layer width, the patent compensates for etching variations. The wiring layer width is specifically designed to be narrower in regions with narrow resistor layers to maintain consistent resistance values without adding dummy structures.
2Manufacturing precision
If wiring layer width is reduced in overlapping regions with narrow resistor layers, then resistance variations are reduced, but manufacturing precision of wiring dimensions becomes more difficult to control
Solution Approach 1:
The patent implements local quality by defining different wiring layer widths for different functional regions. The wiring layer comprises a first region with a first width overlapping first resistor layers, and a second region with a second width (smaller than the first) overlapping second resistor layers. This localized differentiation allows precise control of resistance values in narrow resistor regions while maintaining easier manufacturing control in other regions.
Data Source
AI summary
A semiconductor device includes resistor layers, and a wiring layer which is disposed at least either above or below the resistor layers. The resistor layers include first resistor layers and second resistor layers each having a width in a first direction smaller than a width of the first resistor layer in a first direction. The wiring layer includes first overlapping regions in which the wiring layer overlaps with the first resistor layers in plan view and second overlapping regions in which the wiring layer overlaps with the second resistor layers in plan view. A value obtained by dividing a total value of areas of the second overlapping regions by a width of the second resistor layer is smaller than a value obtained by dividing a total value of areas of the first overlapping regions by a width of the first resistor layer.