Resistor-Based Phase Interpolator for Low-Power Precise Timing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional phase interpolators face challenges in achieving low power consumption and high performance due to the need for current sources and bias circuits, which lead to increased power consumption and startup delays, and struggle with balancing precision, circuit area, and power consumption.

Innovation Solution

A phase interpolator design that eliminates the need for current sources and bias circuits by using resistors to control charging and discharging currents, allowing operation with low voltage and reducing gate capacitance, while also improving Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) through switch configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If current sources and bias circuits are used to control charging and discharging currents, then the phase interpolator can achieve precise phase control, but the power consumption increases and startup delays occur

Engineering Contradiction:
Improvephase control precisionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent extracts and removes the current source and bias circuit from the phase interpolator architecture. Instead of using active current sources, the invention employs passive resistors to control the charging and discharging currents of the capacitor, thereby eliminating the need for bias circuits and reducing power consumption while maintaining phase control functionality

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces expensive and power-consuming current sources with simple, low-cost resistors. The resistors serve as disposable, passive elements that control current flow without requiring complex biasing circuits, significantly reducing both power consumption and circuit complexity

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Measurement precision

If current sources and bias circuits are used to control charging and discharging currents, then the phase interpolator can achieve precise phase control, but startup delays occur due to bias circuit initialization

Engineering Contradiction:
Improvephase control precisionVSAvoidstartup delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent extracts and removes the bias circuit from the phase interpolator architecture. Instead of using active current sources that require bias circuit initialization, the invention employs passive resistors to control the charging and discharging currents of the capacitor, thereby eliminating the need for bias circuits and reducing startup delays

Inventive Principle:
Principle #2Taking out (Extraction)

3Use of energy by moving object

If MOS transistor gate length is increased to reduce charging/discharging current, then power consumption is reduced, but gate capacitance becomes larger leading to increased power consumption

Engineering Contradiction:
Improvepower consumptionVSAvoidperformance
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent replaces the active MOS transistor-based current control mechanism with a passive resistor-based system. Instead of relying on MOS transistor dimensions (gate length and channel width) to control current, the invention uses resistors with specific resistance values to control the charging and discharging currents, avoiding the trade-off between current reduction and capacitance increase

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the control parameter from MOS transistor physical dimensions (gate length L and channel width W) to resistor resistance values. By using resistors with appropriately selected resistance values, the system can control charging/discharging currents without the conflicting effects of increased gate capacitance that occur when MOS transistor gate length is increased

Inventive Principle:
Principle #35Parameter changes

4Use of energy by moving object

If channel width is reduced to reduce charging/discharging current, then current is reduced, but variation increases resulting in degraded performance

Engineering Contradiction:
Improvepower consumptionVSAvoidperformance variation
Core Design Contradiction:
Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The patent replaces the active MOS transistor-based current control mechanism with a passive resistor-based system. Instead of relying on MOS transistor dimensions (gate length and channel width) to control current, the invention uses resistors with specific resistance values to control the charging and discharging currents, avoiding the trade-off between current reduction and capacitance increase

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables low-voltage operation with reduced power consumption, faster startup times, and improved linearity, effectively balancing precision and circuit area considerations.

Implementation Method 1

a capacitor having one end coupled to the intermediate line

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

Each circuit unit comprises: a resistor and a first path arranged in series between the intermediate line and the second line

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS10483956B2Phase interpolator, timing generator, and semiconductor integrated circuit
Publication Date: 2019.11.19 ROHM CO LTD
  • US10483956B2 patent drawing
  • US10483956B2 patent drawing
  • US10483956B2 patent drawing

AI summary

During a period in which a first signal S1 and second signal S2 are both set to a first level, an initializing circuit initializes a capacitor voltage. Multiple circuit units are coupled in parallel between an intermediate line and a second line. An output circuit generates an output signal SOUT that changes level when the capacitor voltage crosses a predetermined threshold value VTH. Each circuit unit includes a resistor Rg and first path arranged in series between the intermediate and second lines and a second path parallel to the first path. The first path is configured to turn on when the first signal S1 is the second level and the corresponding bit of an input code is a first value. The second path is configured to turn on when the second signal S2 is the second level and the corresponding bit of the input code is a second value.