Resistor-Assisted Ring Oscillator for Low-Sensitivity PLL Clocks
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Solution Overview
Problem
Existing integer-N PLL architectures face challenges in optimizing performance for high-frequency applications, particularly concerning phase noise, jitter, and power consumption, which degrade clock signal stability and accuracy in GHz frequency ranges.
Innovation Solution
A resistor-assisted supply-sensitive ring oscillator with a delay cell and compensation circuitry is integrated into PLLs, using transmission gates with unequal strengths and poly resistors to mitigate supply-induced fluctuations, enhancing stability and reducing jitter without increasing power consumption or silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If integer-N PLL architecture is used for high-frequency applications, then frequency multiplication capability is achieved, but phase noise and jitter increase
Solution Approach 1:
The delay cell is segmented into multiple inverters (first, second, third inverters) with progressively decreasing transistor widths. This segmentation allows each inverter stage to contribute differently to the overall delay, enabling precise control of the VCO frequency while maintaining signal integrity and reducing phase noise accumulation across stages
Solution Approach 2:
Each inverter stage is assigned different transistor width ratios (first inverter: 2:1, second inverter: 1.5:1, third inverter: 1:1) to optimize local delay characteristics. This local quality variation ensures that critical stages have appropriate drive strength to minimize jitter while achieving the required frequency multiplication
2Speed
If delay cell transistor sizes are reduced for higher frequency operation, then frequency range is extended, but supply sensitivity increases
Solution Approach 1:
The PMOS and NMOS transistors in each inverter are designed with asymmetric width ratios (2:1, 1.5:1, 1:1) rather than symmetric sizing. This asymmetry optimizes the delay balance and reduces supply voltage sensitivity by compensating for mobility differences between PMOS and NMOS devices, allowing higher frequency operation with reduced supply-induced frequency variations
Solution Approach 2:
The delay cell incorporates controllable delay elements that can dynamically adjust their delay characteristics. This dynamic adjustment capability allows the circuit to maintain optimal performance across varying supply conditions and frequency ranges, reducing supply sensitivity while extending the operational frequency range
3Speed
If conventional ring oscillator is used, then clock signal generation is achieved, but supply-induced frequency variations cause deterministic jitter
Solution Approach 1:
The delay compensation circuitry continuously monitors the delay of the main delay path and generates compensating signals to counteract supply-induced variations. This feedback mechanism detects frequency deviations caused by supply changes and actively corrects them, significantly reducing deterministic jitter while maintaining stable clock signal generation
Solution Approach 2:
The delay compensation circuitry anticipates and counteracts supply-induced delay variations before they significantly impact the output frequency. By applying preliminary compensation based on predicted supply variations, the system prevents deterministic jitter from developing, maintaining clock quality under varying supply conditions
Data Source
AI summary
Disclosed is a Phase-Locked Loop (PLL) with an improved ring oscillator 200. The Phase-Locked Loop (PLL) comprises a delay cell 100. The delay cell 100 may further comprise a main cell 102. Further a delay compensation circuitry 104, is integrally connected with the main cell 102. The Phase-Locked Loop (PLL) comprises a ring oscillator 200 connected with the delay circuit 100. Further the ring oscillator 200 is configured to be supply sensitive and assisted with a resistor. The ring oscillator 200 is connected to the delay cell 102 via the delay compensation circuitry 104. Further the ring oscillator 200 comprises a plurality of stages 202, and each stage from the plurality of stages 202 is cross-coupled with a next or an adjacent stage from the plurality of stages 202.