Resistor Segmentation for Cross-Point Memory Spike Suppression
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Solution Overview
Problem
Current memory devices experience current spikes during selection, which can cause damage to memory cells due to parasitic capacitance discharge, leading to reliability issues such as read disturb and endurance degradation, especially for cells near access line drivers.
Innovation Solution
Incorporating resistors between access line portions and vias in a cross-point memory array to increase the resistance path for parasitic capacitance discharge, thereby reducing the magnitude of current spikes and minimizing impact on normal memory cell operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are accessed using conventional access lines without additional resistance elements, then the memory device achieves simpler structure and lower manufacturing cost, but current spikes occur during selection due to parasitic capacitance discharge, causing damage to memory cells and reliability degradation
Solution Approach 1:
A resistor is introduced as an intermediary element between the access line and the memory cell. This resistor acts as a mediator that limits the discharge current from parasitic capacitance during memory cell selection, preventing harmful current spikes while maintaining normal read/write operations. The resistor is positioned specifically at the intersection of the access line and bit line, where it suppresses the harmful discharge path without interfering with the intended signal paths.
2Reliability
If resistors are added to suppress current spikes, then memory cell reliability is enhanced, but the device complexity and manufacturing process become more complicated
Solution Approach 1:
The resistor is merged with the existing bit line structure at the cross-point intersection. Rather than being a completely separate component, the resistor is integrated into the bit line routing, sharing the same physical space and manufacturing layer structure. This merging approach allows the resistor to be formed using similar deposition and patterning processes as the bit line itself, reducing the need for additional manufacturing steps.
Solution Approach 2:
The resistor value is carefully selected to change the electrical parameters of the access path. By adjusting the resistance value, the design optimizes the suppression of current spikes while minimizing the impact on normal read/write operations. The resistance parameter is tuned to provide sufficient current limiting during parasitic discharge events without creating excessive voltage drops during legitimate memory operations.
3Productivity
If memory density is increased without adding resistance elements, then the memory array achieves higher capacity, but current spikes become more severe due to increased parasitic capacitance and closer cell spacing
Solution Approach 1:
The access line is effectively segmented by the resistor into distinct regions: one region leading to the memory cell and another region continuing along the bit line. This segmentation isolates the parasitic capacitance discharge path from the main memory cell access path. The resistor creates an electrical boundary that prevents discharge current from one segment from affecting memory cells in other segments, enabling higher density packing without proportional increases in current spike severity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of resistors effectively suppresses current spikes, enhancing memory cell reliability and allowing for increased memory density without altering the memory cell structure, and can be applied to various cross-point technologies.
Implementation Method 1
Incorporating resistors between access line portions and vias in a cross-point memory array to increase the resistance path for parasitic capacitance discharge, thereby reducing the magnitude of current spikes
Data Source
AI summary
Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.