Resistor Structure for Integrated Circuit Using STI
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Solution Overview
Problem
The degradation or removal of dummy gate material during aggressive chemical mechanical planarization (CMP) in FET fabrication impedes its effectiveness as a resistive coupling between wires in integrated circuits.
Innovation Solution
A resistor structure is formed using a shallow trench isolation (STI) region with a resistive material above a portion of the STI, a gate structure horizontally displaced from the resistive material, an insulative barrier contacting the resistive material, and contacts within the barrier to ensure the resistive material's integrity and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If aggressive CMP is used during FET fabrication, then manufacturing precision and planarity are improved, but the dummy gate material is degraded or removed
Solution Approach 1:
The patent extracts the resistive material from the dummy gate structure by forming openings within the gate structure to isolate and remove specific portions of the gate material, converting it into a separate resistive element that is protected from CMP degradation
Solution Approach 2:
The patent performs preliminary actions by forming the openings and isolating the resistive material portion of the gate structure before the CMP process occurs, ensuring that the resistive material is protected from degradation during subsequent aggressive CMP steps
2Adaptability or versatility
If dummy gate material is retained for resistive coupling, then circuit functionality is improved, but subsequent CMP processes degrade or remove the material
Solution Approach 1:
The patent introduces an intermediary protective structure by forming openings and isolating the resistive material, creating a protected intermediate state that allows the material to serve its resistive coupling function while being shielded from CMP degradation
Data Source
AI summary
Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods. The resistor structure may include: a shallow trench isolation (STI) region on a substrate; a resistive material above a portion of the shallow trench isolation (STI) region; a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material; an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, an upper surface of the insulative barrier being substantially coplanar with an upper surface of the gate structure; and a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material.