Resistor-String DAC Layout for High-Voltage Source Driver Area Reduction
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Solution Overview
Problem
Existing digital-to-analog converters (DACs) in source drivers for display devices face challenges in reducing chip area due to the need for high voltage endurance, leading to increased size and complexity, especially when handling gradation voltages with significant amplitude differences.
Innovation Solution
A DAC design incorporating a resistor string, pass transistors, and a decoder that groups pass transistors by gradation voltage values, allowing for efficient voltage control and amplification, reducing the need for large devices by using well bias voltages to manage voltage differences between maximum and minimum gradation voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DAC is designed to endure high voltages (e.g., 10V) to handle gradation voltages with large amplitude differences, then voltage endurance is improved, but the device area increases significantly due to larger channel length and width requirements
Solution Approach 1:
The pass transistors are divided into multiple groups based on the gradation voltage values they handle. Each group is further divided into first and second subgroups with different transistor types (PMOS and NMOS). This segmentation allows each transistor group to be optimized for its specific voltage range, enabling the use of smaller transistors overall while maintaining the required voltage endurance for the full 10V range.
Solution Approach 2:
Different types of pass transistors (PMOS vs NMOS) are used in different groups based on the specific gradation voltage values. This local optimization allows each transistor to be sized appropriately for its operating conditions rather than designing all transistors for the maximum voltage, significantly reducing the overall chip area while maintaining reliability.
2Reliability
If the channel length and width are increased to improve voltage endurance, then the device can handle higher voltages, but the manufacturing precision requirements increase and the device complexity increases
Solution Approach 1:
The pass transistors are segmented into multiple groups based on gradation voltage ranges, with each group using appropriately sized transistors. This segmentation reduces the need for uniformly large transistors across all voltage ranges, simplifying the overall device configuration while maintaining voltage endurance through localized optimization.
Solution Approach 2:
Different transistor types and sizes are used in different groups based on local voltage requirements. This local quality approach optimizes each transistor for its specific operating conditions, reducing overall device complexity compared to using uniformly large transistors designed for maximum voltage endurance.
3Reliability
If all pass transistors are designed to handle the maximum voltage range, then voltage endurance is improved, but the area and device complexity increase unnecessarily
Solution Approach 1:
The pass transistors are divided into multiple groups according to the gradation voltage values they output. Each group handles a specific voltage range, allowing transistors to be sized appropriately for their specific function rather than all transistors being oversized to handle the maximum voltage range, thus reducing overall chip area while maintaining necessary voltage endurance.
Solution Approach 2:
Different transistor types (PMOS and NMOS) are selectively used in different groups based on the specific gradation voltage values. This local optimization ensures each transistor is sized and typed appropriately for its operating conditions, reducing the overall chip area compared to designing all transistors for maximum voltage endurance.
Data Source
AI summary
A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.