Resistor Triggered Bidirectional ESD Clamp
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ESD clamps for semiconductor devices and integrated circuits are limited in their ability to provide bidirectional protection, are sensitive to manufacturing variations, and do not easily accommodate varying trigger voltages, leading to inefficiencies and increased costs.
Innovation Solution
The development of a bi-directional ESD clamp using two mirror-coupled transistor stages without a Zener diode, featuring resistors between the base and emitter of each transistor stage, allowing for serial coupling of multiple stages to achieve higher trigger voltages and improved manufacturing robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a Zener diode is used to trigger the ESD clamp, then the trigger voltage is determined by the Zener breakdown voltage, but the device becomes sensitive to manufacturing variations and does not easily accommodate varying trigger voltages
Solution Approach 1:
The patent replaces the Zener diode triggering mechanism with a resistor-based triggering mechanism. The trigger voltage is now determined by the resistor value and the transistor characteristics rather than Zener breakdown voltage. This allows for easier adjustment of trigger voltage by simply changing the resistor value, and the system becomes less sensitive to manufacturing variations because resistors can be more precisely controlled during manufacturing compared to Zener diode breakdown voltages.
2Reliability
If a unidirectional ESD clamp design is used, then the circuit is simpler, but it cannot provide protection against ESD events from both directions
Solution Approach 1:
The patent designs the ESD clamp using a bipolar transistor with resistor triggering that can operate in both forward and reverse directions. The same basic circuit topology provides protection against ESD events regardless of polarity, making the device universal. This achieves bidirectional protection without requiring separate clamp circuits for each direction, thus not significantly increasing overall circuit complexity.
3Adaptability or versatility
If multiple ESD clamp stages are used to achieve higher trigger voltages, then the trigger voltage can be increased, but the chip area increases
Solution Approach 1:
The patent employs a modular ESD clamp stage design where identical circuit blocks can be stacked in series. Each stage contributes to the overall trigger voltage through series connection. This segmentation allows for scalable design where the same compact module is reused multiple times, achieving higher trigger voltages in a systematic way while minimizing chip area through modular reuse of optimized circuit blocks.
4Reliability
If a large resistor is used to trigger the bipolar transistor, then sufficient voltage is developed to bias the emitter-base junction into conduction, but the inherent base resistance and contact resistance interfere with normal operation
Solution Approach 1:
The patent extracts the triggering function into a separate, dedicated resistor component that is specifically designed for ESD triggering purposes. This external triggering resistor is distinct from the inherent base resistance and contact resistance, allowing it to be optimized for triggering reliability without compromising normal operation. The separation of triggering function from the transistor's inherent characteristics resolves the interference problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides efficient bi-directional ESD protection, reduces chip area requirements, and allows for adjustable trigger voltages, enhancing the reliability and cost-effectiveness of semiconductor devices by minimizing sensitivity to manufacturing variations and enabling flexible voltage settings.
Implementation Method 1
Resistor 29 is used to trigger bipolar transistor 25 into conduction when an ESD event occurs. When an ESD event arrives across terminals 22, 23 the collector-base voltage rises very rapidly and a small but finite leakage current begins to flow through the reverse biased collector base junction and through resistor 29. By using a value for resistor 29 that is large compared to the inherent base resistance, sufficient voltage is developed across resistor 29 to bias the emitter-base junction into conduction
Implementation Method 2
Zener diode 130 can also exhibit some small inherent resistance. The purpose of resistance 19 in ESD clamp 21 is not to provide triggering, since this is provided by Zener diode 130 but to keep base 28 and emitter 26 at substantially the same potential unless there is an ESD event. When the voltage across terminals 22, 23 rises beyond a predetermined limit, Zener diode 130 turns on, thereby switching bipolar transistor 25 into conduction and desirably clamping the voltage across terminals 22, 23 at a level below a value capable of damaging circuit core 24
Data Source
AI summary
An electrostatic discharge (ESD) protection device (41, 51, 61, 71, 81) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (41, 41′, 41″; 71, 71′, 71″), each stage (41, 41′, 41″; 71, 71′, 71″) comprising first (T1, T1′, T1″, etc.) and second transistors (T2, T2′, T2′″ etc.) having a common collector (52, 52′, 52″) and first (26, 26′, 26″) and second (36, 36′, 36″) emitters providing terminals (32, 42; 32′, 42′; 32″, 42″) of each clamp stage (41, 41′, 41″; 71, 71′, 71. A first emitter (25) of the first stage (41, 71) couples to the common terminal (23) and a second emitter (42″) of the last stage (41″, 71′) couples to the I/O terminals (22). Zener diode triggers are not used. Integrated external ESD trigger resistors (29, 29′, 29″; 39, 39′, 39″) (e.g., of poly SC) are coupled between the base (28, 28′, 28″; 38, 38′, 38″) and emitter (26, 26′, 26″; 36, 36′, 36″) of each transistor (T1, T1′, T1″; T2, T2′, T2″). Different resistor values (e.g., ˜0.5 k to 150 k Ohms) give different ESD trigger voltages. Cascading the clamp stages (41, 41′, 41″; 71, 71′) gives even higher trigger voltages. The ESD trigger resistances (29, 29′, 29″; 39, 39′, 39″) are desirably located outside the common collector-isolation wall (741, 742, 743; 741′, 742′, 743″) surrounding the transistors (T1, T1′, T1″; T2, T2′, T2″).