Resistor Wire Layout for Lower Parasitic Capacitance in Semiconductors
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Solution Overview
Problem
As semiconductor device dimensions decrease, there is a need to reduce parasitic capacitance in resistors, which existing technologies have not effectively addressed.
Innovation Solution
A semiconductor device structure and manufacturing method that includes a resistor wire made of conductive material, overlapping dummy gate structures and diffusion regions, with series-connected capacitances formed between the resistor wire and the substrate, reducing parasitic capacitance by using a specific layout and interlayer dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If resistor wire is formed over underlying structures in conventional semiconductor devices, then the device can be manufactured with standard processes, but parasitic capacitance between the resistor wire and substrate remains high
Solution Approach 1:
An intermediate layer is introduced between the resistor wire and the substrate. This intermediate layer serves as a mediator that reduces the parasitic capacitance between the resistor wire and substrate while maintaining the electrical connection. The intermediate layer acts as a buffer that decouples the capacitive coupling, thereby reducing the harmful parasitic effect without compromising the device's functional reliability.
Solution Approach 2:
The capacitance reduction is achieved by segmenting the direct capacitive coupling path into multiple stages through the intermediate layer structure. The resistor wire capacitance is divided and distributed through the intermediate layer, reducing the overall parasitic capacitance effect on the substrate.
2Productivity
If semiconductor device dimensions are decreased to improve integration density, then more devices can be packed in the same area, but parasitic capacitance of resistors increases relative to the reduced scale
Solution Approach 1:
The solution moves from a two-dimensional planar configuration to a three-dimensional vertical structure by introducing an intermediate layer between the resistor wire and substrate. This vertical dimensioning allows the resistor wire to be positioned at a different height above the substrate, reducing the parasitic capacitance while maintaining the same planar footprint and thus preserving integration density.
3Ease of manufacture
If traditional resistor configurations are used, then manufacturing is simpler with fewer additional layers, but parasitic capacitance cannot be reduced below a certain threshold
Solution Approach 1:
The intermediate layer is formed as part of the interlayer dielectric structure during the standard semiconductor manufacturing process sequence. By incorporating the capacitance-reducing structure into the existing manufacturing flow rather than adding separate steps, the ease of manufacture is maintained while achieving parasitic capacitance reduction.
Data Source
AI summary
A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.