Semiconductor Resistor Wire Layout Using Dummy Fin-Gate Overlap
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Solution Overview
Problem
In semiconductor devices, the layout of resistor wires is inefficient, leading to increased variations in resistivity as device dimensions decrease, and existing layouts do not effectively reduce the area occupied by resistor arrays.
Innovation Solution
The placement of dummy fin and gate structures under resistor wires, with additional interlayer dielectric layers between the resistor wire and dummy gate structures, reduces the area occupied by resistor arrays and minimizes resistivity variations by embedding the resistor wires in multiple interlayer dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional resistor wire layouts are used, then the device dimensions can be maintained, but the area occupied by resistor arrays increases and resistivity variations increase
Solution Approach 1:
The patent embeds resistor wires within multiple interlayer dielectric layers (first ILD layer, second ILD layer) rather than placing them only on the surface. This vertical stacking approach reduces the planar area occupied by resistor arrays while maintaining their electrical functionality, directly addressing the area reduction goal.
Solution Approach 2:
The resistor wires are nested within the multi-layer dielectric structure, with the first resistor wire embedded in the first ILD layer and the second resistor wire embedded in the second ILD layer. This nesting approach allows compact integration and reduces the overall area required for resistor arrays.
2Manufacturing precision
If traditional resistor wire layouts are used, then the layout simplicity is maintained, but the resistivity variations increase due to inefficient placement
Solution Approach 1:
By utilizing the vertical dimension with multiple ILD layers, the patent achieves better resistivity control without significantly complicating the manufacturing process. Each layer can be formed using standard semiconductor fabrication techniques, making the approach scalable.
Solution Approach 2:
The patent applies different dielectric materials or properties to different layers (first ILD layer, second ILD layer) to optimize local electrical characteristics. This allows tailored control of resistivity and electrical fields in different regions of the device.
3Area of stationary object
If resistor wires are placed only on the surface, then the manufacturing process is simple, but the area efficiency is poor
Solution Approach 1:
The patent transitions from two-dimensional surface placement to three-dimensional embedding within multiple layers. This vertical integration dramatically improves area efficiency while using conventional layer-by-layer fabrication methods that are already standard in semiconductor manufacturing.
Data Source
AI summary
A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.