Resistor Wire Layout With Series Capacitance for Dense Semiconductors
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Solution Overview
Problem
In semiconductor devices, the decreasing dimensions lead to increased parasitic capacitance in resistors, which affects the performance and efficiency of integrated circuits and large-scale integration systems, necessitating a reduction in parasitic capacitance.
Innovation Solution
A semiconductor device structure and manufacturing method involving a resistor wire made of conductive material, where two capacitances are formed in series between the resistor wire and the underlying diffusion regions and substrate, reducing overall parasitic capacitance by using dummy gate structures and interlayer dielectric layers to optimize the layout and placement of the resistor wire.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are decreased, then the integration density is improved, but the parasitic capacitance of resistors increases
Solution Approach 1:
The patent segments the capacitance path by introducing an intermediate layer between the resistor wire and the substrate, dividing the original single capacitance into multiple series capacitances. This segmentation reduces the overall parasitic capacitance while maintaining the compact device structure needed for high integration density.
Solution Approach 2:
The patent introduces an intermediate layer as a mediator between the resistor wire and the substrate. This intermediate layer acts as a capacitance divider, creating series-connected capacitances that reduce the total parasitic capacitance without requiring larger device dimensions, thus maintaining high integration density.
2Object-generated harmful factors
If the parasitic capacitance is reduced by increasing the distance between resistor wire and substrate, then the parasitic capacitance decreases, but the device area increases
Solution Approach 1:
The patent solves the contradiction by adding a vertical dimension (intermediate layer) rather than increasing horizontal distance. This creates series capacitance paths through the vertical stack, reducing parasitic capacitance without expanding the device footprint, thus maintaining compact area while achieving lower parasitic capacitance.
Solution Approach 2:
The patent embeds the intermediate layer within the existing device structure stack, nesting it between the resistor wire and substrate. This nested configuration reduces parasitic capacitance through series capacitance division while maintaining the compact vertical integration, avoiding any increase in device area.
3Ease of manufacture
If conventional resistor structures are used, then the manufacturing process is simple, but the parasitic capacitance is high
Solution Approach 1:
The patent applies preliminary action by forming the intermediate layer during the standard manufacturing process sequence, before final resistor patterning. This allows the capacitance-reducing structure to be integrated without requiring additional manufacturing steps, maintaining ease of manufacture while reducing parasitic capacitance.
Solution Approach 2:
The intermediate layer serves multiple functions: it acts as a capacitance divider to reduce parasitic capacitance, while also serving as part of the standard interlayer dielectric structure. This multi-functionality allows parasitic capacitance reduction without adding manufacturing complexity, as the same layer performs both capacitance management and structural roles.
Data Source
AI summary
A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.