Semiconductor Resistor Wire Layout With Tunable Sheet Resistance
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Solution Overview
Problem
As semiconductor device dimensions decrease, there is a need for more flexible resistor wire designs to accommodate various resistance values, which existing resistor wire layouts fail to provide effectively due to limited adjustability in sheet resistance and layout patterns.
Innovation Solution
The solution involves forming resistor wires with adjustable sheet resistance by varying the deposition parameters of metallic layers, such as TiN or TaN, and using multiple layers with different resistivity values, and surface treatments like oxidation or nitridation to achieve desired resistance values, allowing for different resistor configurations at the same vertical level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional resistor wire layouts are used, then manufacturing is simple, but adaptability for different resistance values is limited
Solution Approach 1:
The patent applies local quality by creating resistor wires with non-uniform cross-sectional areas along their length. Specifically, the resistor wire includes a first portion and a second portion with different cross-sectional areas, resulting in different resistivity values in different segments. This allows a single resistor wire to provide multiple resistance values locally, enhancing adaptability without requiring multiple separate resistor structures or complex layout patterns.
2Adaptability or versatility
If diffusion regions are used to form resistors, then manufacturing is straightforward, but design flexibility is limited
Solution Approach 1:
The patent transitions from two-dimensional planar resistor designs to three-dimensional structures by varying the cross-sectional area of the resistor wire along its length. This dimensional change allows resistance values to be controlled not only through planar geometry but also through vertical cross-sectional variations, providing an additional degree of freedom for resistance adjustment and significantly enhancing design flexibility.
Solution Approach 2:
The resistor wire is formed as a composite structure with different cross-sectional areas in different portions, effectively creating a composite resistor with spatially varying properties. This composite structure allows different segments to contribute different resistance values, enabling flexible resistance design while maintaining a single continuous wire structure that is compatible with standard manufacturing processes.
3Adaptability or versatility
If multiple resistor patterns are used to achieve desired resistance, then resistance values can be adjusted, but layout complexity increases
Solution Approach 1:
The patent merges multiple resistance functions into a single resistor wire structure by creating portions with different cross-sectional areas along its length. Instead of using multiple separate resistor patterns that would require complex routing and connections, the invention combines different resistance values into one continuous wire, simplifying the layout while maintaining resistance adjustability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible resistor wire design by allowing for various resistance values and improved pattern fidelity, enhancing the flexibility of semiconductor device circuit design and manufacturing processes.
Implementation Method 1
a blanket layer of a resistance material is formed over the first dielectric layer
Implementation Method 2
the surface region of the blanket layer is treated to make a resistivity of the surface region different from a remaining region of the blanket layer
Data Source
AI summary
A semiconductor device includes a transistor structure disposed over a substrate, a first interlayer dielectric (ILD) layer disposed over the transistor structure, a second ILD layer disposed over the first ILD layer, and a first resistor wire disposed on the second ILD layer, and a second resistor wire disposed on the second ILD layer. A sheet resistance of the first resistor wire is different from a sheet resistance of the second resistor wire.