Resistorless Master Bias Current Circuit
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Solution Overview
Problem
Prior art master bias current generators are sensitive to silicon process variation and power supply variations due to the use of polysilicon resistors, leading to significant current variations, which are costly to mitigate with external resistors or trimming methods.
Innovation Solution
The proposed master bias current generator uses PMOS and NMOS transistors with specific aspect ratios and diode-connected bipolar transistors to generate a reference current, eliminating the need for on-chip resistors and reducing variability by leveraging well-controlled semiconductor process parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon resistors are used in the master bias current generator, then the circuit can be implemented with standard CMOS process, but the current varies significantly due to silicon process variation
Solution Approach 1:
The patent removes the polysilicon resistor from the circuit entirely and replaces it with a resistorless bias generation approach using only transistors. This extraction of the problematic component eliminates the source of high variability while maintaining CMOS compatibility.
Solution Approach 2:
The patent changes the fundamental parameters of the bias generation circuit by transitioning from a resistor-based design to a transistor-based design. This involves changing the operating principles and device parameters to achieve process-insensitive current generation.
2Manufacturing precision
If external resistors or trimming methods are used to reduce current variation, then the current precision improves, but the device complexity and cost increase
Solution Approach 1:
The patent eliminates the need for external resistors and trimming circuits by implementing a fully integrated resistorless bias generator using only standard CMOS transistors, thereby reducing device complexity and cost while maintaining high precision.
Solution Approach 2:
The circuit achieves self-regulation through the inherent characteristics of the transistor configuration, automatically compensating for process variations without requiring external trimming or adjustment mechanisms.
3Device complexity
If the master bias current generator uses traditional current mirrors with diode-connected transistors, then the circuit structure is simple, but the power supply rejection ratio is poor
Solution Approach 1:
The patent employs dynamic biasing techniques where the bias current is generated through active transistor regulation rather than static resistor-based setting, enabling the circuit to dynamically reject power supply variations while maintaining structural simplicity.
Data Source
AI summary
A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size parameter coupled to the current source and a first diode having a second size parameter coupled to the first transistor. The second reference leg includes a second transistor having a third size parameter less than the first size parameter coupled to the current source and a second diode having a fourth size parameter greater than the second size parameter coupled to the second transistor.