Resizing Circuitry Using Circular Shift Registers
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Solution Overview
Problem
Integrated circuits face challenges in resizing data units efficiently across nodes due to the 'convolution' problem, where buffer entries are overwritten prematurely, leading to data loss and increased circuit area and power consumption when dealing with non-power-of-2 ratios of data sections.
Innovation Solution
The implementation of circular shift registers with different arrangements of storage circuits, including convolution-avoidance and masking storage circuits, to control the writing of data sections to buffers, preventing premature overwriting and allowing for efficient resizing of data units across nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional buffer writing control is used for resizing data units, then the resizing function can be implemented, but buffer entries are overwritten prematurely causing data loss
Solution Approach 1:
A token bit is introduced as an intermediary control mechanism to manage buffer entry writing. The token bit circulates through circular shift registers and enables or disables writing to specific buffer entries at appropriate times, preventing premature overwriting while maintaining data integrity during resizing operations
Solution Approach 2:
The system dynamically changes the write-enable parameter of buffer entries based on the position of the token bit in the circular shift register. By controlling whether each buffer entry is enabled for writing at each clock cycle, the system prevents data loss without requiring additional complex control logic
2Reliability
If additional buffer space is provided to prevent premature overwriting, then data loss is prevented, but circuit area and power consumption increase
Solution Approach 1:
The token bit is positioned in advance in specific stages of the circular shift register to predict and prevent premature overwriting before it occurs. By controlling the write-enable signal proactively based on token bit position, the system prevents data loss without needing additional buffer space
Solution Approach 2:
The buffer writing capability is made dynamic rather than static. Each buffer entry's write-enable status changes dynamically based on the token bit position, allowing the same buffer space to be reused efficiently across different clock cycles without premature overwriting
3Reliability
If additional buffer space is provided to prevent premature overwriting, then data loss is prevented, but power consumption increases
Solution Approach 1:
The control function for preventing premature overwriting is extracted from the buffer structure itself and implemented separately using circular shift registers and token bit control. This separation allows the buffer to maintain its original size while still preventing data loss through intelligent control, reducing power consumption compared to enlarging the buffer
4Adaptability or versatility
If conventional resizing control is used, then the resizing function is simple, but it cannot handle non-power-of-2 ratios efficiently
Solution Approach 1:
The circular shift register-based control mechanism serves multiple functions: it tracks the position of data sections, controls write-enable signals for buffer entries, and adapts to different resizing ratios. This universal control structure handles both power-of-2 and non-power-of-2 ratios efficiently without requiring separate control logic for each case
Data Source
AI summary
Resizing circuitry comprises at least one buffer having buffer entries each corresponding to one of at least two shift registers, each shift register comprising storage circuits connected in a ring to transfer a token bit between storage circuits. Selection circuitry controls, based on the shift registers, writing of data sections of input data units having a first number of data sections to the buffer(s), to form output data units having a second number of data sections. For a given buffer entry corresponding to a given shift register, depending on whether the token bit is stored in a first or second subset of storage circuits, the selection circuitry controls writing of a selected data section of a received input data unit to the given buffer entry or prevents overwriting of the given buffer entry. At least two of the shift registers have different relative arrangements of the first and second subsets of storage circuits.