Resolution Scaler Using Shift Adders to Reduce Hardware Size
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Solution Overview
Problem
Conventional resolution scalers for digital display devices require expensive multipliers and take longer to operate due to their complex structure, making them inefficient in scaling high-resolution frame data for display devices with lower resolutions.
Innovation Solution
A resolution scaler design that eliminates multipliers by using a counter controller and pixel scaler with shift adders to generate scaled pixel data through shifting and adding operations, reducing hardware size and operational time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multipliers are used in the resolution scaler to generate scaled pixel data, then the scaling accuracy is improved, but the hardware size increases and operational speed decreases
Solution Approach 1:
The patent replaces expensive multiplier circuits with cheaper shift adder circuits that use bit-shifting and addition operations. This substitution maintains sufficient scaling accuracy while dramatically reducing hardware cost and operational time, as shift adders are computationally simpler and faster to execute than multipliers
Solution Approach 2:
The patent substitutes the mechanical multiplication operation with a combination of bit-shifting and addition operations. This is achieved by expressing the scaling weight as a sum of powers of 2, allowing the multiplication to be performed through sequential shifting and adding operations that are faster and require less hardware
2Measurement precision
If multipliers are used in the resolution scaler to generate scaled pixel data, then the scaling accuracy is improved, but the hardware size and implementation cost increase
Solution Approach 1:
The patent replaces expensive multiplier circuits with cheaper shift adder circuits that use bit-shifting and addition operations. This substitution maintains sufficient scaling accuracy while dramatically reducing hardware cost and operational time, as shift adders are computationally simpler and faster to execute than multipliers
Solution Approach 2:
The patent segments the scaling weight into multiple binary components (powers of 2), allowing the multiplication operation to be broken down into separate shift and add operations. This segmentation enables the use of simpler circuitry while achieving the same functional result
3Adaptability or versatility
If conventional pixel scaling methods are used, then the resolution difference between frame data and display device is handled, but the operational time is excessive
Solution Approach 1:
The patent uses periodic bit-shifting operations with different shift amounts corresponding to different power-of-2 components of the scaling weight. This periodic shifting pattern, combined with accumulation, enables fast computation of the scaled pixel values without requiring complex multiplication circuits
Solution Approach 2:
The patent pre-calculates the binary decomposition of the scaling weight and prepares the shift amounts in advance. This preliminary preparation allows the actual pixel scaling operation to proceed rapidly through a sequence of pre-planned shift and add operations, minimizing operational time
Data Source
AI summary
A resolution scaler of the present invention uses a shift adder instead of a multiplier for scaling an input resolution. The resolution scaler is provided with a counter controller and a pixel scaler. The counter controller outputs a weight to the pixel scaler. The pixel scaler includes a first shift adder for outputting the first shift value by adding a plurality of first shift arguments generated by shifting the current pixel data, a second shift adder for outputting the second shift value by adding a plurality of second shift arguments generated by shifting the previous pixel data, and an adder for outputting the scaled pixel data by adding the first shift value and the second shift value.