Resolver Decoder Hardware Filtering for Real-Time Shaft Angle Estimation
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Solution Overview
Problem
Existing resolver decoders for traction motor control in electrical vehicles require high hardware costs and computing power to accurately estimate the motor shaft angle, which is a critical parameter for efficient motor operation.
Innovation Solution
A digital resolver decoder circuit with integrated hardware filters and a hardware rectifier that processes digital samples of sine and cosine signals from the resolver, using finite impulse response (FIR) filters and a hardware rectifier to calculate the motor shaft angle with reduced computational load on the CPU, thereby lowering hardware costs and improving real-time performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional resolver decoders are used to accurately estimate the motor shaft angle, then measurement precision is improved, but device complexity and computing power requirements increase
Solution Approach 1:
The patent replaces complex software-based angle estimation algorithms with a dedicated hardware resolver decoder circuit that performs the same function through specialized electronic components. This hardware implementation includes signal conditioning circuits, coordinate transformation units, and angle calculation modules that physically compute the motor shaft angle from resolver signals, eliminating the need for high-power general-purpose processors while maintaining measurement precision.
Solution Approach 2:
The resolver decoder circuit is designed as an integrated multi-functional unit that simultaneously performs signal filtering, coordinate transformation, angle calculation, and error compensation within a single hardware architecture. This universal design consolidates multiple separate processing functions into one device, reducing overall system complexity while preserving accurate angle estimation capability.
2Measurement precision
If more computational tasks are performed by the CPU to improve angle estimation accuracy, then measurement precision is improved, but productivity and real-time performance deteriorate
Solution Approach 1:
The patent segments the angle estimation function from the main CPU by implementing a dedicated resolver decoder circuit. This separation divides the control system into independent functional modules: the hardware decoder handles real-time angle calculation from resolver signals, while the CPU focuses on higher-level control algorithms. This segmentation enables parallel processing where the hardware circuit operates independently at high speed without burdening the CPU, thus improving both precision and real-time performance.
Solution Approach 2:
The resolver decoder circuit acts as an intermediary between the resolver sensor and the CPU control system. It receives raw resolver signals, performs real-time signal conditioning and angle computation, then outputs processed angle data to the CPU. This intermediary hardware layer filters and pre-processes signals before CPU intervention, reducing the computational burden on the CPU while ensuring accurate real-time angle measurement is achieved through dedicated hardware processing.
Data Source
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AI summary
A resolver decoder circuit (130) includes: a first filter circuit (115A) configured to calculate a first weighted sum of a first digital signal over a predetermined period of time, where the first digital signal includes first digital samples of a first analog signal (106A) from a sine winding of a resolver; a second filter circuit (115B) configured to calculate a second weighted sum of a second digital signal over the pre-determined period of time, where the second digital signal includes second digital samples of a second analog signal (106B) from a cosine winding of the resolver, where the first (106A) and the second (106B) analog signals are configured to be induced by a sine signal applied to an input winding of the resolver; and a rectifier (113) configured to generate a first output and a second output by adjusting (603) a first sign of the first weighted sum and adjusting a second sign of the second weighted sum, respectively.