Resolver Integral Demodulation with Half-Period ADC Switching
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Solution Overview
Problem
Existing demodulation algorithms for resolver position determination are time-consuming, resource-intensive, and produce inaccurate results due to the need for simultaneous sampling of three feedback signals using separate analog to digital converters, leading to phase delays and increased processing time.
Innovation Solution
A digital signal processing system utilizing N2HET timers to generate a resolver excitation signal and zero-crossing signals, which controls data movement into memory buffers, allowing simultaneous collection of resolver sine and cosine samples at different times, reducing the need for simultaneous sampling and integrating only half periods to determine quadrant position.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simultaneous sampling of three feedback signals using separate ADCs is used, then measurement completeness is improved, but processing time and resource consumption increase
Solution Approach 1:
The patent combines the sampling of sine and cosine feedback signals into a single ADC by using a multiplexer that switches between signals based on zero-crossing detection of the excitation signal. This merging approach eliminates the need for multiple simultaneous ADCs while maintaining measurement accuracy, thereby reducing processing time and resource consumption.
Solution Approach 2:
The system performs preliminary zero-crossing detection of the excitation signal to generate select signals that control the multiplexer switching. This preliminary action allows the ADC to be pre-configured for the next signal to be sampled, eliminating waiting time and ensuring continuous accurate measurement without requiring simultaneous sampling infrastructure.
2Measurement precision
If simultaneous sampling of three feedback signals using separate ADCs is used, then measurement completeness is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple signal sampling functions into a single ADC by using a multiplexer controlled by zero-crossing detection. This consolidation reduces the number of ADCs from three to one, significantly simplifying the device architecture while maintaining the ability to accurately measure all feedback signals through sequential sampling synchronized to the excitation signal cycles.
Solution Approach 2:
The single ADC is designed to perform multiple sampling functions by switching between different feedback signals (sine and cosine) based on zero-crossing events. This multi-functional approach allows one ADC to replace three dedicated ADCs, reducing device complexity while maintaining measurement completeness across all signal channels.
3Loss of information
If separate ADCs are used for each feedback signal, then signal acquisition completeness is improved, but resource consumption increases
Solution Approach 1:
The patent combines multiple signal acquisition functions into a single ADC resource, eliminating the need for multiple parallel ADC operations. By using a multiplexer controlled by zero-crossing detection, the system ensures that all feedback signals (sine and cosine) are fully captured sequentially, maintaining information completeness while consuming significantly less power than running multiple simultaneous ADCs.
4Measurement precision
If full period integration is performed for demodulation, then measurement accuracy is improved, but processing time increases
Solution Approach 1:
The patent performs integration over only half-periods of the excitation signal rather than full periods, leveraging the symmetry properties of sine and cosine waves. By integrating during half-periods defined by zero-crossing points and using appropriate sign multiplication, the system achieves the same measurement accuracy with half the processing time, effectively applying partial action that suffices for the measurement goal.
Data Source
AI summary
A digital signal processing system to determine a position of a resolver includes a digital signal processor that includes first timer and second timer. The first timer creates a resolver excitation signal from a series of samples and creates an incrementing Crossing signal each time the resolver excitation signal crosses zero. When the Crossing signal has a first value, a multiplexer provides resolver sine signals to an analog to digital converter to convert the resolver sine signal to a series of digital sine samples, and the second timer stores the series of digital sine samples in a sine sample buffer. When the Crossing signal has a second value, the multiplexer provides the resolver cosine signal to the analog to digital converter to convert the resolver cosine signal to a series of digital cosine samples, and the second timer stores the series of digital cosine samples in a buffer.