Resolver Hall Decoding Circuit Using Adder-Based Position Mapping
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Solution Overview
Problem
Existing methods for converting resolver data to Hall code format in brushless DC motors require complex circuitry or programmable devices, which are undesirable due to the need for design verification procedures, especially in high-reliability applications like aircraft systems.
Innovation Solution
A method and device that generate Hall code data by adding predetermined numbers to the position data, discarding any carry out, and determining Hall code bits based on the most significant bits of these sums, eliminating the need for complex circuitry and programmable devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a programmable memory device is used to map resolver data to Hall code, then the conversion accuracy is improved, but the device complexity and verification requirements increase
Solution Approach 1:
The patent replaces complex programmable memory devices with a purely mathematical addition-based conversion method. The Hall code is generated by adding predetermined constants to the resolver position data and truncating to the appropriate number of bits, eliminating the need for complex lookup tables or programmable logic while maintaining accurate conversion.
Solution Approach 2:
The patent changes the conversion approach from memory-based lookup to arithmetic operation-based calculation. By using addition of predetermined constants and bit truncation, the system transforms the conversion process into a simple mathematical operation that is both accurate and easy to implement in hardware.
2Measurement precision
If digital comparators are used to implement the mapping, then the conversion accuracy is improved, but the device complexity and number of components increase
Solution Approach 1:
The patent replaces multiple digital comparator devices with a single addition operation. Instead of using comparators to determine which Hall code range the resolver data falls into, the system simply adds a predetermined constant and truncates the result, achieving the same mapping function with far fewer components.
Solution Approach 2:
The patent extracts only the essential mathematical relationship needed for conversion (addition and truncation) while eliminating unnecessary comparison logic. This extraction of the core conversion mechanism reduces the number of devices required while maintaining the accuracy of the mapping.
3Adaptability or versatility
If a programmable device is used for mapping, then the adaptability is improved, but the verification time and cost increase
Solution Approach 1:
The patent replaces programmable devices with a fixed arithmetic circuit implementation. The predetermined constants are hard-coded into the addition operation, eliminating the need for programming and verification while maintaining the mapping functionality. This approach trades programmability for verification simplicity.
Solution Approach 2:
The patent segments the conversion process into simple, verifiable arithmetic operations (addition and truncation) rather than using a monolithic programmable device. This segmentation makes the system easier to verify and validate, as each operation can be independently tested and confirmed.
Data Source
AI summary
A device for converting position data to Hall code data includes a data input for providing the position data, a data output for providing the Hall code data, a first adder circuit operative to provide a sum of a first predetermined number and a value provided by the data input, and a memory circuit for storing a plurality of data. A most significant bit of the data input is provided to a first storage location of the memory circuit, and a most significant bit of the first adder circuit's sum is provided to a second storage location of the memory circuit. An output of the memory circuit is operatively coupled to the data output.