Resolver Integral Demodulation Using Zero-Crossing Timer Sampling
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Solution Overview
Problem
Existing demodulation algorithms for resolver position determination are time-consuming, resource-intensive, and inaccurate due to the need for simultaneous sampling of three feedback signals using separate analog to digital converters, resulting in phase delays and less accurate results.
Innovation Solution
A digital signal processing system employing N2HET timers to generate a resolver excitation signal and Select/Zero Crossing signal, which controls data routing to memory buffers, allowing synchronized acquisition of sine and cosine samples for half periods and eliminating the need for excitation signal monitoring during demodulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simultaneous sampling of three feedback signals using separate ADCs is used, then complete signal acquisition is achieved, but processing time increases and accuracy decreases due to phase delays
Solution Approach 1:
The patent extracts only the necessary sine and cosine samples from the resolver feedback signals, storing them in separate buffers without requiring simultaneous sampling of all three signals. This selective extraction eliminates the time-consuming simultaneous sampling requirement while maintaining measurement accuracy.
Solution Approach 2:
The system performs preliminary sampling of sine and cosine signals into separate buffers before demodulation, using timer-generated triggers synchronized to zero-crossings. This preliminary action prepares data in advance, eliminating the need for time-critical simultaneous sampling during actual position determination.
2Reliability
If separate ADCs are used for simultaneous sampling, then all feedback signals are captured, but system complexity and resource consumption increase
Solution Approach 1:
The patent merges the sampling function into a single ADC that sequentially samples sine and cosine signals based on timer-generated triggers. This consolidation eliminates the need for multiple simultaneous ADCs, reducing system complexity while maintaining complete signal acquisition through time-division multiplexing.
Solution Approach 2:
A single ADC is made multi-functional by using it to sample both sine and cosine signals at different times, controlled by timer-generated triggers. This universal approach allows one ADC to perform the work of multiple ADCs, reducing hardware complexity while maintaining acquisition completeness.
3Measurement precision
If excitation signal monitoring is performed during demodulation, then accurate quadrant determination is achieved, but processing resources increase
Solution Approach 1:
The system determines quadrant information preliminarily by monitoring zero-crossings of the excitation signal and using this information to trigger appropriate sampling sequences. This preliminary quadrant determination eliminates the need for resource-intensive excitation signal monitoring during actual demodulation, reducing processing resources while maintaining accuracy.
Solution Approach 2:
The patent introduces timer-generated Select/Zero Crossing signals as intermediaries that carry quadrant information without requiring direct excitation signal monitoring during demodulation. These intermediary signals provide the necessary quadrant information to the sampling and processing system, reducing the computational burden while maintaining determination accuracy.
Data Source
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AI summary
A digital signal processing system to determine a position of a resolver includes a digital signal processor that includes first timer and second timer. The first timer creates a resolver excitation signal from a series of samples and creates an incrementing Crossing signal each time the resolver excitation signal crosses zero. When the Crossing signal has a first value, a multiplexer provides resolver sine signals to an analog to digital converter to convert the resolver sine signal to a series of digital sine samples, and the second timer stores the series of digital sine samples in a sine sample buffer. When the Crossing signal has a second value, the multiplexer provides the resolver cosine signal to the analog to digital converter to convert the resolver cosine signal to a series of digital cosine samples, and the second timer stores the series of digital cosine samples in a buffer.