Trap Circuits for Capacitively Coupled Resonant Clock Crosstalk
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Solution Overview
Problem
CMOS technology-based digital circuits face limitations in device size and high power consumption, especially due to static power dissipation and current leakage even when inactive, leading to inefficiencies in high-performance digital systems.
Innovation Solution
The implementation of a superconducting integrated circuit with trap circuits and capacitively-coupled resonant clock networks, using Josephson junctions and AC power to reduce crosstalk and eliminate static power dissipation, leveraging metamaterial transmission lines for efficient clock signal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS technology is used for digital circuits, then device integration is achieved, but power consumption increases due to static power dissipation and current leakage
Solution Approach 1:
The patent transitions from CMOS technology operating at DC voltage to superconducting logic circuits operating with AC voltage. This parameter change fundamentally alters the power consumption characteristics, eliminating static power dissipation and current leakage while maintaining device integration capability through Josephson junctions and resonant clock networks
Solution Approach 2:
The patent replaces the DC-based CMOS mechanical/electrical system with an AC-based superconducting logic system. This substitution uses alternating current to drive Josephson junctions, replacing the traditional DC voltage operation of CMOS transistors, thereby eliminating the harmful effects of static power dissipation and leakage current
2Ease of operation
If Josephson junctions are coupled via capacitors in a resonant clock network, then clock signal distribution is achieved, but crosstalk between adjacent junctions occurs
Solution Approach 1:
The patent introduces trap circuits as intermediary elements between adjacent Josephson junctions coupled via capacitors. These trap circuits act as mediators that selectively filter and attenuate unwanted signal frequencies, allowing the resonant clock network to distribute clock signals effectively while preventing crosstalk between adjacent junctions
Solution Approach 2:
The patent extracts and removes harmful crosstalk signals from the clock network by using trap circuits to identify and eliminate unwanted signal components. The trap circuits selectively remove frequencies corresponding to crosstalk while preserving the desired clock signal frequencies, thereby cleaning the signal environment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces crosstalk and power consumption by attenuating unwanted signals and eliminating static power dissipation, leading to improved performance and efficiency in digital circuits.
Implementation Method 1
a first capacitor for coupling a first Josephson junction to a first node of a first clock line
Implementation Method 2
a first trap circuit coupled between the first capacitor and the first Josephson junction, where the first trap circuit is configured to attenuate any signals generated by a triggering of the first Josephson junction
Implementation Method 3
a resonant clock network capacitively-coupled to a first Josephson junction and a second Josephson junction
Implementation Method 4
a first Josephson junction via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first Josephson junction
Data Source
AI summary
Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.