Resonant Converter Hard Switching Prevention via Timer Control
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Solution Overview
Problem
Resonant converters face hard switching issues during startup, leading to potential transistor destruction due to reverse recovery stress and shoot-through conditions, particularly when the high-side transistor is turned on while the body diode of the low-side transistor is still conducting.
Innovation Solution
A control circuit with timers sets specific time periods for pre-charging the bootstrap capacitor and maintaining transistors off to avoid hard switching, ensuring the body diode has time to recover before the high-side transistor is turned on, using a timer circuit to generate control signals for the half-bridge circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the high-side transistor is turned on immediately after the low-side transistor is turned off during startup, then the switching speed is improved, but hard switching conditions occur causing reverse recovery stress and potential transistor destruction
Solution Approach 1:
The patent applies preliminary action by implementing a delay mechanism that prevents the high-side transistor from turning on immediately after the low-side transistor turns off. A timer circuit generates a delayed enable signal that activates the high-side transistor only after a predetermined time interval, ensuring the body diode has recovered from reverse recovery. This preliminary timing control eliminates hard switching conditions and reverse recovery stress, protecting the transistor from damage while maintaining reliable operation.
2Reliability
If a dead time is added after each transistor is turned off, then reverse recovery stress is reduced, but the switching frequency is limited and efficiency decreases
Solution Approach 1:
The patent implements preliminary action by pre-calculating and programming the exact delay period into a timer circuit before startup. The timer is configured with a predetermined time value that is sufficient for diode recovery but minimized to allow high switching frequencies. This pre-set timing approach ensures optimal protection without excessive dead time, enabling the converter to operate at high frequencies while maintaining transistor reliability.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the delay time parameter based on operating conditions. The timer circuit can modify the delay period according to temperature, load conditions, or diode characteristics, optimizing the balance between protection and switching frequency. By varying this critical timing parameter, the system achieves both transistor protection and high productivity across different operating scenarios.
3Reliability
If the bootstrap capacitor is pre-charged for a longer time period, then the high-side transistor can be turned on safely, but the startup time is extended
Solution Approach 1:
The patent applies preliminary action by pre-charging the bootstrap capacitor during a controlled time interval before enabling the high-side transistor. The timer circuit monitors the charging process and enables the transistor as soon as the capacitor reaches sufficient voltage, minimizing the pre-charge time while ensuring safe operation. This preliminary timing control eliminates unnecessary delays while maintaining reliable transistor activation.
Data Source
AI summary
A circuit includes a timer circuit configured to generate a first control signal defining a first time period and a second control signal defining a second time period. A controller is configured to control a high-side and a low-side transistor of a half-bridge circuit in response to the first and second control signals only during a first switching cycle of the half-bridge circuit. The half-bridge circuit includes a bootstrap capacitor coupled to a node between the high-side and low-side transistors. The controller turns on the low-side transistor for the first time period during the first switching cycle and configured turns off the low-side and the high-side transistors for the second time period during the first switching cycle.