Resonant Rotary Clocking with RTWOs for Low-Skew GPU Synchronization
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Solution Overview
Problem
Existing clocking architectures in graphics processing units (GPUs) face challenges with clock design complexity due to multi-die, multi-process, and low latency requirements, necessitating a robust, low-power, low-skew, and low-jitter solution that can be scaled across various product segments.
Innovation Solution
Implementing resonant rotary clocking architectures using rotary traveling wave oscillators (RTWOs) and oscillator arrays (ROAs) with fractional dividers and custom reset synchronizers to distribute deterministic, high-speed clocks across large dies, and utilizing rectangular rotary oscillators for die-to-die synchronization in 3D stacked systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clocking architectures are used in GPUs, then clock distribution can be achieved, but clock design complexity increases exponentially due to multi-die, multi-process, and large synchronous domain requirements
Solution Approach 1:
The patent divides the large synchronous domain into multiple smaller synchronous domains, each with its own clock source. This segmentation reduces the complexity of clock distribution across the entire GPU while maintaining reliability through localized clock management. Each domain can be independently optimized and synchronized with adjacent domains.
Solution Approach 2:
The patent transitions from traditional 2D clock distribution to a 3D clocking architecture that utilizes vertical interconnects (through-silicon vias) for clock signal propagation. This dimensional change enables more efficient clock distribution across multi-die stacks, reducing the complexity associated with long horizontal clock routes.
2Reliability
If clock signals are distributed across large dies and 3D stacked systems, then synchronization can be achieved, but clock skew and jitter increase
Solution Approach 1:
The patent implements local clock sources within each synchronous domain rather than distributing a single global clock signal. This allows each domain to have optimized local clock characteristics, reducing cumulative skew and jitter. Critical paths receive locally-generated clock signals with deterministic phase relationships.
Solution Approach 2:
The patent incorporates phase-locked loops (PLLs) and delay-locked loops (DLLs) that use feedback mechanisms to continuously monitor and adjust clock phase and frequency. This feedback control compensates for process variations, temperature changes, and voltage fluctuations, maintaining low skew and jitter across the system.
3Power
If traditional clocking solutions are implemented, then clock signals can be generated, but power consumption increases
Solution Approach 1:
The patent segments the clocking system into multiple independent clock domains, each with its own low-power clock source. This allows power to be distributed across many small, efficient clock generators rather than requiring one or two high-power global clock sources, reducing overall power consumption while maintaining clock signal generation capability.
Solution Approach 2:
The patent employs voltage-controlled oscillators (VCOs) and programmable frequency dividers that can dynamically adjust operating parameters based on workload requirements. This allows the system to reduce clock frequency and voltage during low-performance periods, significantly lowering power consumption while maintaining the ability to generate high-frequency clocks when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution provides low-skew, low-jitter, and low-power clocking with deterministic phase points, enabling efficient synchronization across large dies and 3D stacked systems, reducing power consumption and improving efficiency in graphics products.
Implementation Method 1
resonant rotary clocking architectures using rotary traveling wave oscillators (RTWOs)
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A rotary oscillator array (ROA) apparatus includes a plurality of rotary traveling wave oscillators (RTWOs) configured to generate a plurality of resonant clock signals. An RTWO of the plurality of RTWOs includes a plurality of inverter cells and a fractional divider. The inverter cells are coupled in parallel to each other between two metal interconnects. The fractional divider is coupled to the two metal interconnects. The fractional divider will output a resonant clock signal of the plurality of resonant clock signals based on a reset-out signal generated by a reset-out terminal of the RTWO.