Resonant Rotary Clocking for Low-Skew Multi-Die Synchronization

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Solution Overview

Problem

Designing a robust, high-speed, low-skew, low-jitter, and low-power clock across chiplet-based systems is challenging due to the complexity of clock synchronization in multi-die systems, particularly in moving away from traditional globally asynchronous locally synchronous (GALS) solutions.

Innovation Solution

Implementing a resonant rotary clocking system using a multi-die system with an interposer and resonant rotary ring structures to distribute synchronized clock signals across dies, eliminating the need for phase-locked loops (PLLs) and delay-locked loops (DLLs) by tapping clock signals at deterministic phase points.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional GALS solutions are used for clock distribution in multi-die systems, then design robustness is improved, but device complexity and verification challenges increase

Engineering Contradiction:
Improveclock distribution robustnessVSAvoiddesign and verification complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the complex PLL and DLL synchronization circuits from the multi-die system by using a resonant clock signal that naturally provides deterministic phase relationships across dies, thereby reducing design and verification complexity while maintaining robustness

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the clock signal parameter from asynchronous or locally-synchronous to a resonant frequency that creates deterministic phase points, fundamentally altering how clock synchronization is achieved and simplifying the overall system design

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If PLLs and DLLs are used for clock synchronization across dies, then clock synchronization accuracy is improved, but area consumption and power usage increase

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoidcircuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent removes the bulky PLL and DLL circuits from the design by using a resonant clock signal that inherently provides the necessary synchronization, eliminating the need for these area-consuming components while maintaining deterministic phase relationships

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The resonant clock signal creates natural phase copies at deterministic intervals around the ring structure, providing synchronized clock edges to multiple dies without requiring additional synchronization circuitry

Inventive Principle:
Principle #26Copying

3Measurement precision

If PLLs and DLLs are used for clock synchronization across dies, then clock synchronization accuracy is improved, but power consumption increases

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent eliminates the power-hungry PLL and DLL circuits by using a resonant clock signal that provides deterministic phase relationships without requiring active synchronization, thereby significantly reducing power consumption while maintaining clock accuracy

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The resonant ring structure self-generates the synchronized clock signals at deterministic phase points without requiring external PLL or DLL circuits, making the system self-sufficient and reducing overall power consumption

Inventive Principle:
Principle #25Self-service

4Device complexity

If traditional clocking methods are used in multi-die systems, then design simplicity is maintained, but operation speed and energy efficiency decrease

Engineering Contradiction:
Improvecircuit design simplicityVSAvoidoperation speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent changes the clock signal to a resonant frequency that enables faster operation by providing deterministic phase points, allowing receivers to sample data at optimal moments and improving overall system speed while maintaining design simplicity

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies D2D circuit design, reduces area and power consumption, and enables faster operation by using resonant clock signals for die-to-die communication, improving energy efficiency and setup margin.

Implementation Method 1

resonant rotary clocking system using a multi-die system with an interposer and resonant rotary ring structures to distribute synchronized clock signals

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentUS20240429865A1Techniques for resonant rotary clocking for die-to-die communication
Publication Date: 2024.12.26 INTEL CORP
  • US20240429865A1 patent drawing
  • US20240429865A1 patent drawing
  • US20240429865A1 patent drawing

AI summary

Various embodiments provide apparatuses, systems, and methods for resonant rotary clocking for die-to-die (D2D) communication in a multi-die system. A base die may include a resonant ring structure to form a plurality of rotary traveling wave oscillators (RTWOs) coupled to one another in a rotary oscillator array (ROA). The ROA may provide synchronized clock signals at deterministic phase points that are tapped from the resonant ring structure. Multiple dies may be coupled to the base die and may receive the tapped clock signals from respective tap points. The clock signals may be used for die-to-die communication and/or other purposes. Other embodiments may be described and claimed.