Piezoelectric Resonator Layout to Suppress Parasitic Capacitance
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Solution Overview
Problem
In existing piezoelectric resonator devices, the arrangement of wiring lines overlapping excitation electrodes leads to increased parasitic capacitance, which deteriorates the electrical characteristics of the oscillator.
Innovation Solution
The resonator device is configured with a frame, first, and second substrates forming a cavity housing a resonator element and semiconductor element, where the first wiring line is positioned to avoid overlapping with the second excitation electrode in a plan view, preventing parasitic capacitance between the wiring lines and excitation electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the wiring line coupled to the second excitation electrode is arranged at a position faced to the first excitation electrode, then the wiring line can be easily routed and connected, but parasitic capacitance increases and electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement where wiring lines overlap excitation electrodes to a three-dimensional configuration using the cavity depth. The wiring line is routed along the inner surface of the second substrate, utilizing the vertical dimension to separate the wiring line from the excitation electrode in the planar view, thereby reducing parasitic capacitance while maintaining connectivity.
Solution Approach 2:
The inner surface of the second substrate serves as an intermediary structure that carries the wiring line. This intermediary allows the wiring line to be electrically connected to the excitation electrode through conductive structures (such as through-holes or conductive paste) while physically separating them in the planar dimension, thus reducing parasitic capacitance effects.
2Reliability
If the wiring line is arranged to avoid overlapping the excitation electrode in plan view, then parasitic capacitance is reduced, but the wiring line routing becomes more complex
Solution Approach 1:
The patent utilizes the third dimension (cavity depth) to simplify the wiring arrangement. By routing the wiring line along the inner surface of the second substrate and using conductive structures to penetrate or contact the excitation electrode from the rear, the patent achieves non-overlapping planar arrangement without significantly increasing routing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the deterioration of electrical characteristics by preventing parasitic capacitance, thereby improving the vibration and electrical performance of the resonator device.
Implementation Method 1
a piezoelectric device provided with a piezoelectric resonator unit which vibrates with a pair of excitation electrodes
Implementation Method 2
a resonator device includes an element substrate having a resonator element which has a first excitation electrode arranged on one surface and a second excitation electrode arranged on another surface
Data Source
AI summary
A resonator device includes an element substrate provided with a resonator element having a first excitation electrode arranged on one surface and a second excitation electrode arranged on another surface, and a frame surrounding the resonator element, a lid substrate bonded to one surface of the frame, a base substrate bonded to another surface of the frame, and a semiconductor element including an oscillation circuit electrically coupled to the resonator element, wherein the frame, the lid substrate, and the base substrate form a cavity for housing the resonator element and the semiconductor element, the base substrate includes a first wiring line which is arranged on a surface faced to the second excitation electrode, and electrically couples the first excitation electrode and the semiconductor element to each other, and the first wiring line is arranged at a position which fails to overlap the second excitation electrode in a plan view.