Resource Interconnect Backdoor and Nested Descriptors

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Solution Overview

Problem

Centralized interconnect architectures in computer processing systems experience bottlenecks when multiple co-processing units try to communicate with the same destination simultaneously, leading to increased data processing latency and reduced throughput.

Innovation Solution

A resource interconnect architecture with a backdoor interconnect and nested descriptors allows for efficient communication between resources, optimizing processing and error handling by enabling alternative communication paths and chaining operations without requiring responses to originate from the initial resource.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a centralized resource interconnect is used to connect multiple co-processing units, then resource sharing and communication are enabled, but bottlenecks occur when multiple units communicate to the same destination simultaneously, increasing latency and reducing throughput

Engineering Contradiction:
Improveresource sharing capabilityVSAvoiddata processing throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent divides the centralized resource interconnect into multiple segmented interconnects, each handling specific traffic flows or destination groups. This segmentation allows parallel communication paths, eliminating the single-point bottleneck while maintaining resource sharing capabilities across the system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an additional dimensional aspect to the interconnect architecture by adding multiple interconnect layers or planes. Instead of a single centralized path, resources can communicate through alternative paths in different dimensions, providing parallelism and reducing latency for simultaneous communications.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If a centralized resource interconnect is used to connect multiple co-processing units, then resource sharing and communication are enabled, but bottlenecks occur when multiple units communicate to the same destination simultaneously, increasing latency

Engineering Contradiction:
Improveresource sharing capabilityVSAvoiddata processing latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent divides the centralized resource interconnect into multiple segmented interconnects, each handling specific traffic flows or destination groups. This segmentation allows parallel communication paths, eliminating the single-point bottleneck while maintaining resource sharing capabilities across the system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary routing decisions and descriptor pre-processing at the source co-processing units. By preparing communication descriptors and selecting optimal paths in advance, the system reduces waiting time and latency when actual data transmission occurs, allowing parallel communication paths to be utilized more efficiently.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7664897B2Method and apparatus for communicating over a resource interconnect
Publication Date: 2010.02.16 CISCO TECHNOLOGY INC
  • US7664897B2 patent drawing
  • US7664897B2 patent drawing
  • US7664897B2 patent drawing

AI summary

A resource interconnect architecture and associated descriptor protocol provides more efficient communication between different resources in a data processing system. One embodiment uses a backdoor interconnect that allows some resources to communicate without using a central resource interconnect. Another embodiment uses nested descriptors that allow operations by different resources to be chained together without having to communicate back to an originating descriptor resource. In another embodiment, the descriptors are generated in hardware or in software. Other embodiments assign priority or privilege values to the descriptors that optimize processing and error handling performance.