Hardware Resource Sharing Optimizer for Streaming Code
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Solution Overview
Problem
Existing code generation systems for hardware description languages struggle to optimize code for hardware resource sharing and streaming while maintaining bit true and cycle accurate results, especially when dealing with overclocking constraints and varying computation latencies.
Innovation Solution
A code generation system that includes an integrity checker, intermediate representation generator, optimization engine, and global scheduler, which utilizes streaming and resource sharing optimizers to transform source models into optimized hardware description code, inserting data unbuffer and demultiplexor blocks to share resources without overclocking, and ensures timing alignment through delay balancing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If hardware resources are shared to reduce resource consumption, then hardware resource efficiency is improved, but timing alignment and computation latency may be compromised
Solution Approach 1:
The system segments the hardware resource sharing problem into multiple independent optimization phases: resource sharing identification, timing analysis, delay calculation, and validation. Each phase handles specific aspects of the contradiction separately, allowing resource sharing to be implemented while timing constraints are systematically managed and validated throughout the transformation process.
Solution Approach 2:
The system performs preliminary timing analysis and delay calculation before finalizing the resource sharing transformation. By calculating required delays in advance and incorporating them into the transformed model, the system ensures that timing alignment is preserved even when resources are shared, thus resolving the contradiction between resource efficiency and timing precision.
2Productivity
If code is optimized for streaming to improve data flow efficiency, then processing throughput is improved, but bit true and cycle accurate results may be compromised
Solution Approach 1:
The system implements feedback mechanisms through validation models that compare the behavior of the transformed streaming-optimized model against the original model. This feedback loop ensures that bit true and cycle accurate results are maintained by detecting and correcting any deviations introduced by streaming optimizations, thus resolving the contradiction between throughput improvement and result precision.
Solution Approach 2:
The system dynamically adjusts the level of streaming optimization applied to different parts of the model based on timing constraints and data flow characteristics. By making the optimization dynamic and adaptive rather than uniform, the system can maximize throughput where safe while preserving bit true and cycle accurate behavior where required, thus resolving the precision-throughput contradiction.
3Reliability
If resources are shared without overclocking to maintain timing constraints, then hardware reliability is improved, but resource sharing flexibility is limited
Solution Approach 1:
The system changes parameters such as delay values, sampling rates, and timing offsets to enable resource sharing while maintaining timing constraints without overclocking. By adjusting these parameters systematically, the system achieves flexible resource sharing that adapts to timing requirements, resolving the contradiction between reliability and flexibility.
4Measurement precision
If the system validates transformed models to ensure bit true results, then result accuracy is improved, but validation time and complexity increase
Solution Approach 1:
The system performs partial validation by focusing on critical paths and key timing constraints rather than exhaustive validation of all model behaviors. This selective validation approach maintains bit true result accuracy for the most important aspects while reducing overall validation time and complexity, thus resolving the contradiction between accuracy and time cost.
Data Source
AI summary
A system and method optimizes hardware description generated from a graphical program or model having oversampling constraints automatically. The system may include a streaming optimizer, a resource sharing optimizer, a delay balancing engine, and a global scheduler. The streaming optimizer may transform vector data paths to scalar or smaller-sized vector data paths. The resource sharing optimizer may replace multiple, functionally equivalent blocks with a single shared block. The delay balancing may insert one or more elements to correct for data path misalignment. The global scheduler may place portions of the program or model into conditional execution sections and create control logic that controls the model sample times or steps that the portions are enabled. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from a modified version of the model that is created.