Response Modification Circuitry for Interconnect Transaction Handling
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Solution Overview
Problem
In complex system-on-chip (SoC) integrated circuits, existing interconnect circuitry faces challenges in managing transaction responses effectively, particularly in scenarios involving coherency protocols, burst transfers, atomic operations, and speculative fetches, where transaction responses need to be modified before reaching the transaction master, requiring efficient identification and modification mechanisms.
Innovation Solution
The implementation of response modification circuitry that stores identification data in a shortlist buffer to identify and modify transaction responses in transit from transaction slaves to transaction masters, allowing for modifications such as dividing burst transactions, indicating atomic operation success, and managing coherency states, while using transaction tracking circuitry to manage identifier reuse and storage efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If interconnect circuitry manages complex transaction protocols (coherency, burst transfers, atomic operations), then transaction management capability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a response modification circuit as an intermediary component between the transaction slave and master. This circuit intercepts transaction responses, modifies them if needed (e.g., converting byte-enable patterns), and forwards them to the master. This mediator approach enables complex protocol management without requiring the entire interconnect circuitry to be overly complex, as the modification functionality is localized to a dedicated circuit.
2Manufacturing precision
If transaction responses are modified in transit, then transaction control precision is improved, but identification and modification overhead increases
Solution Approach 1:
The response modification circuit is configured to modify transaction responses as they pass through the interconnect circuitry, before reaching the transaction master. By performing the modification action preliminarily in transit, the circuit avoids the need for additional retrieval and modification steps at the master side, thereby reducing overall time loss despite the added identification requirement.
3Adaptability or versatility
If burst transactions are divided into smaller transfers, then data transfer flexibility is improved, but transaction processing overhead increases
Solution Approach 1:
The patent implements burst transaction division by intercepting byte-enable patterns in transaction responses and splitting them into smaller, manageable units. The response modification circuit segments the original burst transfer into multiple smaller transfers, each with its own byte-enable pattern, allowing flexible data reordering and retrieval without requiring the entire burst to be processed as a single unit. This segmentation approach improves transfer flexibility while managing processing overhead through localized modification.
Data Source
AI summary
Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.