Restricted Coherency Protocol for Virtualized Domain Memory Latency
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Solution Overview
Problem
Cache coherency protocols in multi-processor systems lead to increased latency due to the need to query and synchronize cache states across multiple processors, which can significantly impact memory operation performance, especially as the number of processors increases.
Innovation Solution
Implementing a restricted coherency protocol within virtualized domains, where each domain has exclusive memory access, allowing processors to bypass downstream caches when operations are within the domain's accessible memory space, reducing the need for inter-domain cache coherence checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full cache coherency protocol is implemented across all processors in a multi-processor system, then cache data integrity is maintained, but memory operation latency increases significantly
Solution Approach 1:
The system segments the multi-processor system into multiple virtualized domains, where each domain has exclusive access to specific memory regions. This segmentation allows the coherency protocol to be applied locally within domains rather than globally across all processors, reducing the scope of coherency checks and lowering memory latency while maintaining data integrity within each domain.
Solution Approach 2:
The patent implements a local coherency protocol that applies different coherency rules to different memory regions based on domain boundaries. Memory regions accessible exclusively by a single domain use a simplified coherency protocol, while shared regions use the full protocol. This local differentiation maintains necessary data integrity while minimizing unnecessary coherency checks that increase latency.
2Productivity
If the number of processors in a multi-processor system is increased to improve computing power, then system capability is enhanced, but memory operation latency increases due to more cache coherence checks
Solution Approach 1:
By segmenting the system into virtualized domains, the patent enables more processors to be added to the system without proportionally increasing coherency check complexity. Each domain can utilize multiple processors that share exclusive access to domain-specific memory regions, allowing the system to scale computing power while maintaining low latency through localized coherency management.
3Speed
If a restricted coherency protocol is implemented to reduce latency, then memory operation speed improves, but cache coherency management complexity increases
Solution Approach 1:
The patent introduces a domain identifier mechanism as an intermediary that automatically determines which coherency protocol to apply based on the memory address being accessed. This intermediary layer simplifies the complexity by providing automatic domain-based protocol selection, allowing the system to benefit from restricted coherency protocols while minimizing the management overhead through automated domain identification and protocol selection.
Data Source
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AI summary
A method of accelerating memory operations using virtualization information includes executing a hypervisor on hardware resources of a computing system. A plurality of domains are created under the control of the hypervisor, are created. Each domain is allocated memory resources that include accessible memory space that is exclusively accessible by that domain. Each domain is allocated one or more processor resources. The hypervisor identifies domain layout information that includes a boundary of accessible memory space of each domain. The hypervisor provides the domain layout information to each processor resource. Each processor resource is configured to implement, on a per domain basis, a restricted coherency protocol based on the domain layout information. The restricted coherency protocol bypasses, relative to the domain, downstream aches when a cache line falls within the accessible memory space of that domain.