Results Processing Circuitry for Computational Memory Arrays
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Solution Overview
Problem
Existing memory systems lack the ability to efficiently combine computational results across multiple bit line sections, limiting their capability to perform complex logical operations and algorithms effectively.
Innovation Solution
The implementation of a processing array with computational memory cells and additional Results Processing (RSP) circuitry that allows for the logical combination of computation results across multiple bit line sections, using dual port SRAM cells to perform operations like AND, NOR, XOR, and XNOR, and utilizing RSP circuitry to generate and store combined results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cells are connected to the same read bit line to perform logical functions, then computational capability is improved, but the ability to combine results across multiple bit line sections is limited
Solution Approach 1:
A dedicated results processing circuit is introduced as an intermediary component between multiple bit line sections and the final output. This circuit receives individual results from each bit line section and combines them using logical operations (AND, OR, NOR, XOR, XNOR) to produce a unified result, thereby enabling effective result combination across multiple sections without overwhelming system complexity
Solution Approach 2:
The results processing circuit is designed with multi-functionality, capable of performing multiple logical operations (AND, OR, NOR, XOR, XNOR) and supporting various computational algorithms. This universal design allows the same circuit structure to handle different computational tasks and combine results from multiple bit line sections flexibly, enhancing adaptability while maintaining manageable complexity
2Stability of the object's composition
If multiple bit line sections execute the same computational algorithm, then consistency is improved, but efficiency in performing complex algorithms is reduced
Solution Approach 1:
The system is segmented into multiple independent bit line sections, each capable of executing the same computational algorithm simultaneously on different data sets. The results processing circuit then combines these parallel results efficiently. This segmentation enables parallel processing while maintaining algorithmic consistency, thereby improving overall productivity without sacrificing uniformity in computation
Solution Approach 2:
Results from multiple bit line sections that execute the same computational algorithm are merged through the results processing circuit. The circuit combines these results using appropriate logical operations to produce a final unified result. This merging process maintains algorithmic consistency while achieving efficient parallel execution of complex algorithms across multiple sections
Data Source
AI summary
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.