RESURF Device Charge Balancing via Sinker and Isolation Wall
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Solution Overview
Problem
Existing RESURF semiconductor devices face challenges in simultaneously optimizing series ON-resistance and breakdown voltage, with restrictive doping and geometry choices, and issues with latch-up problems and parasitic bipolar transistors, particularly in double RESURF devices.
Innovation Solution
The introduction of N-type sinker regions or plugs in LDMOS transistors to enhance charge balancing, along with the use of N-type isolation walls and variable resistance bridges to adjust electric potentials, allowing for more flexible doping and thickness variations, thereby improving breakdown voltage and reducing ON-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If traditional RESURF doping and geometry choices are used to optimize breakdown voltage, then breakdown voltage is improved, but series ON-resistance increases and device design flexibility is reduced
Solution Approach 1:
The patent applies parameter changes by introducing adjustable doping concentrations in the drift region and body region, along with variable thickness parameters, to independently optimize both breakdown voltage and ON-resistance without being constrained by traditional fixed geometry choices. This enables continuous tuning of electrical characteristics to achieve simultaneous optimization.
Solution Approach 2:
The patent implements dynamic charge balancing through adjustable doping profiles and geometric parameters that can be modified during device design and manufacturing. This dynamic approach allows the device to achieve optimal performance across different operating conditions while maintaining design flexibility.
2Ease of manufacture
If traditional RESURF doping and geometry choices are used to optimize series ON-resistance, then series ON-resistance is reduced, but breakdown voltage decreases and device design flexibility is reduced
Solution Approach 1:
The patent uses parameter changes by adjusting the doping concentration in the drift region and body region, along with thickness variations, to independently control ON-resistance while maintaining adequate breakdown voltage. This decoupling of parameters allows simultaneous optimization of both characteristics.
Solution Approach 2:
The patent applies local quality by creating spatially varying doping profiles within the drift and body regions, where different local areas have optimized doping concentrations to simultaneously reduce ON-resistance in the channel area while maintaining breakdown voltage in the depletion region.
3Reliability
If double RESURF structures are used to improve charge balancing, then RESURF action is enhanced, but latch-up problems and parasitic bipolar transistor issues arise
Solution Approach 1:
The patent extracts or removes the problematic double RESURF structure that causes latch-up and parasitic bipolar transistor issues, while retaining the essential charge balancing function through a simplified single RESURF structure with optimized doping profiles. This eliminates the harmful effects while preserving the beneficial charge balancing action.
Solution Approach 2:
The patent converts the potential harm of excessive charge balancing (which can cause latch-up) into a benefit by implementing precise, controlled charge balancing through optimized doping profiles. This controlled approach achieves the necessary charge balance without creating the conditions for parasitic transistor activation.
Data Source
AI summary
Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.