RESURF Layer Arrangement for LDMOS Breakdown Voltage
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Solution Overview
Problem
LDMOS devices with double RESURF structures face breakdown issues between the body and buried isolation layer due to increased field stress, which limits breakdown voltage and degrades ESD and SOA performance, and previous solutions introduce fabrication challenges or degrade performance.
Innovation Solution
The implementation of a RESURF layer arrangement between the isolation contact and the body region, which distributes electrostatic potential more uniformly, reducing voltage stress between the body and isolation regions, and allows partial lifting of the isolation potential without additional dopant implantation procedures, thereby enhancing breakdown voltage without compromising manufacturing costs or ESD/SOA performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If biasing isolation regions at drain voltage is applied to deplete n-type and p-type regions, then breakdown voltage is improved, but field stress between body and buried isolation layer increases causing breakdown
Solution Approach 1:
The isolation structure is segmented into multiple regions: a first isolation region with first conductivity type and a second isolation region with second conductivity type. This segmentation allows independent control of potential in different isolation zones, enabling the second isolation region to be biased at drain voltage for depletion while the first isolation region maintains lower potential, thus reducing field stress between body and buried isolation layer.
Solution Approach 2:
The first isolation region acts as an intermediary between the body region and the second isolation region. It mediates the potential distribution by maintaining a potential lower than the drain voltage, thereby reducing the direct field stress that would otherwise exist between the body and the high-potential second isolation region, while still allowing the second isolation region to provide the necessary depletion effect.
2Reliability
If previous efforts to address source/body-based breakdown are introduced, then breakdown voltage is improved, but fabrication complexity increases or ESD and SOA performance degrades
Solution Approach 1:
The isolation regions are merged with the drift region in such a way that they form an integrated structure where the drift region and isolation regions share common boundaries and doping profiles. This merging allows the isolation structure to provide breakdown voltage enhancement without requiring separate fabrication steps or additional processing complexity, as the same dopant implantation procedures used for the drift region also define the isolation regions.
3Reliability
If double RESURF structure is used, then electrostatic potential distribution is improved, but field stress between body and isolation regions increases
Solution Approach 1:
Different regions of the isolation structure are assigned different conductivity types and potential levels according to their local functional requirements. The first isolation region has one conductivity type and maintains lower potential near the body, while the second isolation region has opposite conductivity type and is biased at drain voltage. This local differentiation optimizes both electrostatic potential distribution and field stress management in different spatial zones.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases breakdown voltage levels while maintaining manufacturing simplicity and performance, allowing for the use of Schottky contacts in high-voltage applications without increasing costs, and improves reliability in scenarios with transient negative potentials.
Implementation Method 1
a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate, the plurality of reduced surface field (RESURF) layers being arranged in a stack between the body region and the isolation contact
Implementation Method 2
The RESURF structure is designed to deplete the drift space of the LDMOS device in both vertical and lateral directions, thereby reducing the electric field near the surface at the drift region
Data Source
AI summary
A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate, a body region disposed in the semiconductor substrate within the doped isolation barrier and in which a channel is formed during operation, an isolation contact disposed at the semiconductor substrate and to which a voltage is applied during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate, the plurality of reduced surface field (RESURF) layers being arranged in a stack between the body region and the isolation contact.