RESURF MOSFET Doping Layout for Breakdown Voltage and Low On-Resistance
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Solution Overview
Problem
Semiconductor devices with RESURF regions face a trade-off between improving breakdown voltage performance and reducing on-resistance, as increasing the length of the RESURF region to enhance breakdown voltage leads to higher on-resistance, and vice versa.
Innovation Solution
Incorporating a semiconductor device with a RESURF region that includes a buried diffusion layer with a higher peak impurity concentration and an additional diffusion layer extending closer to the low-side circuit, dispersing electric field concentration across these regions to improve breakdown voltage performance while reducing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the length of the RESURF region is increased to improve breakdown voltage performance, then the on-resistance of the MOSFET increases
Solution Approach 1:
The patent applies local quality by creating distinct impurity concentration zones within the RESURF region. Specifically, it forms a first impurity region with a first peak concentration and a second impurity region with a second peak concentration, where the concentration profiles are optimized locally to achieve both high breakdown voltage and low on-resistance. This local differentiation allows each region to contribute optimally to the overall performance without requiring the entire RESURF region to be extended.
Solution Approach 2:
The patent employs parameter changes by precisely controlling the impurity concentration parameters (N1, N2, X1, X2) of different regions within the RESURF structure. By adjusting these parameters - specifically setting N1×X1 < N2×X2 while maintaining appropriate relationships between concentrations and depths - the patent optimizes the electric field distribution to simultaneously achieve high breakdown voltage and low on-resistance, resolving the traditional trade-off.
2Loss of energy
If the impurity concentration of the RESURF region is increased to reduce on-resistance, then the breakdown voltage performance deteriorates
Solution Approach 1:
The patent segments the RESURF region into multiple impurity concentration zones - specifically a first impurity region and a second impurity region with different peak concentrations and depth profiles. This segmentation allows the first region to contribute to breakdown voltage maintenance while the second region provides lower resistance, enabling both objectives to be achieved simultaneously without compromising either parameter.
Solution Approach 2:
The patent creates a composite impurity concentration profile within the RESURF region by combining multiple doping regions with different characteristics. The first impurity region with concentration N1 and depth X1 is combined with a second impurity region with concentration N2 and depth X2, forming a composite structure that exhibits both high breakdown voltage characteristics and low resistance characteristics, effectively resolving the trade-off between these two parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively improves the trade-off between breakdown voltage performance and on-resistance by dispersing electric field concentration, resulting in enhanced performance characteristics compared to conventional designs.
Implementation Method 1
dispersing electric field concentration across these regions to improve breakdown voltage performance
Implementation Method 2
a third region of the second conductivity type formed at least in a bottom portion of the second region close to the high-side circuit, having a higher peak concentration of impurities than the second region
Data Source
AI summary
Provided is a semiconductor device including: an N-type diffusion layer being a second region, formed in a surface portion of a P-type diffusion layer being a first region, to function as a RESURF region; an N-type buried diffusion layer being a third region formed in a bottom portion of the second region, close to a high-side circuit; and a MOSFET using the second region as a drift layer. The MOSFET includes a thermal oxide film formed between an N-type diffusion layer being a fourth region serving as a drain region and an N-type diffusion layer being a sixth region serving as a source region, and an N-type diffusion layer being a seventh region formed below the thermal oxide film. The seventh region has an end portion close to a low-side circuit, being closer to the low-side circuit than an end portion of the third region close to the low-side circuit.