Semiconductor Oxide Layout for High-Voltage RESURF and PIP Capacitors
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Solution Overview
Problem
Existing semiconductor manufacturing methods face challenges such as damage to shallow trench isolation and LOCOS field oxide regions, and exceeding thermal budget limitations during the formation of angled dielectric layers in high voltage devices, leading to issues like notching and increased on-resistance.
Innovation Solution
A manufacturing method that uses high voltage polysilicon hard masks and a first electrode plate to form two-stage inclined oxide regions, avoiding additional photomasks and reducing thermal processes, while integrating high and low voltage devices and a poly silicon-insulator-poly silicon (PIP) capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If an angled dielectric layer is formed to implement RESURF technique, then device breakdown voltage is improved, but additional thermal oxidation processes exceed the thermal budget
Solution Approach 1:
The patent performs preliminary oxidation to form a thick field oxide layer before device fabrication. This pre-formed oxide layer serves as the foundation for the angled dielectric structure, eliminating the need for subsequent high-temperature oxidation processes that would exceed the thermal budget. The field plate is then formed on this pre-existing oxide layer to achieve the RESURF effect.
Solution Approach 2:
The patent segments the dielectric layer formation into distinct stages: a thick field oxide layer formed by preliminary oxidation, and an additional angled dielectric layer formed by low-temperature oxidation or deposition. This segmentation allows the bulk of the oxide thickness to be achieved before device processing, avoiding thermal budget constraints during critical device fabrication steps.
2Strength
If an angled dielectric layer is formed to implement RESURF technique, then device breakdown voltage is improved, but wet etching processes cause shallow trench isolation corner loss (notching)
Solution Approach 1:
The patent introduces a specially designed field plate structure that acts as an intermediary element between the gate and the substrate. This field plate extends over the shallow trench isolation regions and provides field control without requiring aggressive wet etching of the isolation oxides. The field plate's geometry is optimized to prevent notching while maintaining the angled dielectric profile for RESURF operation.
Solution Approach 2:
The patent applies different oxide thicknesses and compositions at different locations: a thick field oxide under the field plate for electrical isolation and field control, and a thinner oxide at the shallow trench isolation corners to prevent notching. This local differentiation allows the angled dielectric structure to provide breakdown voltage enhancement without compromising the precision of the shallow trench isolation corners.
3Strength
If multiple thermal oxidation processes are used to form angled dielectric layer, then device breakdown voltage is improved, but the thermal budget is exceeded
Solution Approach 1:
The patent performs the major oxidation step before device fabrication begins. This preliminary action creates the bulk of the field oxide thickness that is needed for breakdown voltage enhancement, so that subsequent device processing steps do not require additional high-temperature oxidation that would consume the thermal budget.
Solution Approach 2:
The patent changes the oxidation parameters from high-temperature, long-duration oxidation (which would exceed thermal budget) to low-temperature, short-duration oxidation or alternative deposition methods for forming the additional angled dielectric layer. This parameter change allows the angled structure to be formed without consuming excessive thermal budget during device fabrication.
4Ease of manufacture
If photoresist stripping during wet etching is performed, then capacitor formation is completed, but shallow trench isolation or LOCOS field oxide regions are damaged
Solution Approach 1:
The patent uses the field plate structure as an intermediary that protects the shallow trench isolation regions during photoresist stripping. The field plate's geometry and material properties are designed to prevent photoresist from adhering to or damaging the isolation regions during the stripping process, while still allowing complete capacitor formation to proceed.
Solution Approach 2:
The patent applies preliminary protective measures to the shallow trench isolation regions before photoresist stripping. This may include forming a protective coating or modifying the isolation region geometry in advance to prevent damage during the capacitor formation process, thereby maintaining isolation integrity while completing capacitor fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method prevents damage to shallow trench isolation and reduces thermal processes, thereby avoiding notching and thermal budget exceedance, enhancing device reliability and performance.
Implementation Method 1
forming a bottom thermal oxide layer on a substrate
Implementation Method 2
forming a chemical vapor deposition (CVD) oxide layer that completely covers the bottom thermal oxide layer
Data Source
AI summary
A manufacturing method of a semiconductor integrated structure having a high voltage device, a low voltage device and a capacitor, includes: forming a bottom thermal oxide layer on a substrate; forming a chemical vapor deposition (CVD) oxide layer; forming a poly silicon hard mask layer; etching the poly silicon hard mask layer to form a high voltage poly silicon hard mask and a first electrode plate simultaneously; etching the CVD oxide layer and using the high voltage poly silicon hard mask and the first electrode plate as etching barrier layers to form a high voltage CVD oxide region and a capacitor CVD oxide region simultaneously; etching the bottom thermal oxide layer and using the high voltage poly silicon hard mask and the first electrode plate as the etching barrier layers to form a high voltage bottom thermal oxide region and a bottom thermal oxide region simultaneously.