RESURF Semiconductor Structure for Low On-Resistance Breakdown Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining high breakdown voltage while reducing on-resistance, particularly due to the trade-off between n-type impurity concentration in the drift region and the presence of a p-type resurf layer.
Innovation Solution
The semiconductor device incorporates a p-type resurf layer that expands laterally to cover the n-type drift region, ensuring the side portions of the resurf layer and drift region are flush, and optionally includes a buried n-type layer to further enhance breakdown voltage and reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If n-type impurity concentration in the drift region is increased to reduce on-resistance, then on-resistance is reduced, but breakdown voltage decreases
Solution Approach 1:
The patent applies local quality by creating a p-type resurf layer with a specific impurity concentration profile only in the drift region, while maintaining different impurity concentrations in other regions. The p-type resurf layer has a gradient structure where the impurity concentration varies from the surface toward the bulk, allowing localized optimization of electrical properties without affecting the entire device structure. This enables reduced on-resistance in the drift region while preserving breakdown voltage through controlled local doping variations.
Solution Approach 2:
The patent utilizes parameter changes by systematically varying the p-type impurity concentration in the resurf layer from the surface toward the bulk of the drift region. The impurity concentration is designed to decrease with depth, creating a gradient that optimizes both on-resistance and breakdown voltage. Additionally, the patent changes the concentration parameters of n-type impurity regions relative to the p-type resurf layer, achieving a balanced electrical characteristic that resolves the contradiction between low on-resistance and high breakdown voltage.
2Reliability
If a p-type resurf layer is formed to prevent electric field concentration, then breakdown voltage is improved, but on-resistance increases
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through a graded p-type resurf layer structure. Instead of a uniform p-type layer, the impurity concentration is optimized to decrease from the surface toward the bulk, creating different local electrical properties. This gradient structure allows the resurf layer to prevent electric field concentration at the surface (improving breakdown voltage) while maintaining lower resistance in deeper regions (reducing on-resistance). The local quality variation enables both functions to coexist without mutual interference.
Solution Approach 2:
The patent applies composite material principles by creating a multi-layered drift region structure comprising the p-type resurf layer with gradient concentration and the underlying n-type drift region. This composite structure combines the field-blocking capability of the p-type layer with the high conductivity of the n-type region, achieving both high breakdown voltage and low on-resistance. The interface between these layers is designed to optimize carrier transport while preventing electric field concentration, effectively combining the benefits of both material types.
Data Source
AI summary
A semiconductor device includes: a first conductivity type substrate; a second conductivity type semiconductor layer formed over the substrate; a second conductivity type drift region formed at a surface portion of the semiconductor layer; a second conductivity type drain region formed at the drift region; a first conductivity type body region formed adjacent to the drift region at the surface portion of the semiconductor layer; a second conductivity type source region formed at the body region; and a first conductivity type resurf layer that expands from a center of the drain region to both sides in a lateral direction along a main surface of the semiconductor device to entirely cover the drift region.