Resynchronization Circuit Phase Detection Migration Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional resynchronization circuits face difficulties in increasing data transfer speed due to limited migration margin as the frequency of the reception-side clock signal increases, as they are designed to hold data at rising or falling edges of the system clock signal, leading to inefficient data latching.
Innovation Solution
A resynchronization circuit that includes a reception timing detection circuit to determine the phase range of the received data signal within one cycle of the reference clock signal, using multiple holding circuits synchronized with different phase ranges of the reference clock signal to hold and output the data at a timing closer to the center of the period, ensuring a sufficient migration margin for faster data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is held at rising or falling edges of the system clock signal in conventional resynchronization circuits, then the circuit structure is simple, but the migration margin decreases as clock frequency increases, making data latching difficult
Solution Approach 1:
The patent divides the clock signal cycle into multiple phase ranges (first phase range and second phase range) and uses separate holding circuits for each phase range. This segmentation allows data to be held at optimal timing within each phase, increasing the migration margin while enabling higher data transfer speeds.
Solution Approach 2:
The patent dynamically selects which holding circuit to use based on the detected phase range of the received data signal. By adaptively changing the holding timing according to the input signal's phase characteristics, the system maintains sufficient migration margin across varying clock frequencies, enabling reliable high-speed data transfer.
2Speed
If the frequency of the reception-side clock signal is increased to achieve faster data transfer, then the data transfer speed increases, but the migration margin decreases making data latching more difficult
Solution Approach 1:
The patent performs preliminary phase detection of the received data signal before the actual data latching operation. By detecting the phase range in advance and pre-selecting the appropriate holding circuit, the system ensures that data latching occurs at optimal timing even at high clock frequencies, maintaining reliability while achieving high speed.
Solution Approach 2:
The patent changes the timing parameter of data latching based on the detected phase range. By adjusting which holding circuit is activated (and thus when data is latched within the clock cycle), the system optimizes the migration margin for high-frequency operation, enabling reliable data transfer at increased clock speeds.
3Reliability
If multiple holding circuits with different phase ranges are used to increase migration margin, then data transfer reliability improves, but the circuit complexity increases
Solution Approach 1:
The patent designs the holding circuits to have identical internal structures, with the only difference being their clock phase ranges. This universal design allows the same circuit block to be reused multiple times with different phase configurations, increasing reliability through redundancy while minimizing the increase in overall circuit complexity.
Solution Approach 2:
The patent segments the clock cycle into distinct phase ranges and assigns dedicated holding circuits to each segment. This segmentation approach systematically manages complexity by organizing the circuit into modular, phase-specific units, making the design more manageable and maintainable while achieving improved migration margin through diversified phase coverage.
Data Source
AI summary
A resynchronization circuit possesses a sufficient migration margin even when the speed of a clock signal used for outputting data is increased, so that the data transfer speed can be increased. In the resynchronization circuit, a determination circuit holds a signal which is determined according to the phase difference between a determination signal and a reference clock signal (determination result). In a synchronization circuit block, a received data signal is held in synchronization with a strobe signal. Then, the received data signal is held in synchronization with a clock signal which has the same frequency as that of the reference clock signal and has a phase determined according to the determination result and output from the resynchronization circuit.